MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 287

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
5-ports_a
MOTOROLA
NOTE:
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 4
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
the port A pins.
1. Writing affects data register, but does not affect input.
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
Data Direction Bit
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
shows the port A I/O logic.
0
1
READ DDRA ($0004)
WRITE DDRA ($0004)
WRITE PORTA ($0000)
READ PORTA ($0000)
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I/O Ports
Table 2. Port A Pin Operation
Figure 4. Port A I/O Circuit
RESET
Input, high-impedance
I/O Pin Mode
Output
Table 2
DDRAx
PAx
summarizes the operation of
Read
Latch
Pin
Access to Data Bit
MC68HC708XL36
Latch
Write
Latch
I/O Ports
(1)
Port A
287
PAx

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