MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 304

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
I/O Ports
MC68HC708XL36
304
NOTE:
DDRH[3:0] — Data Direction Register H Bits
Avoid glitches on port H pins by writing to the port H data register before
changing the data direction register H bits from 0 to 1.
Figure 25
When bit DDRHx is a logic 1, reading address $000B reads the PHx data
latch. When bit DDRHx is a logic 0, reading address $000B reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
the port H pins.
1. Writing affects data register, but does not affect input.
These read/write bits control port H data direction. Reset clears
DDR[3:0], configuring all port H pins as inputs.
Freescale Semiconductor, Inc.
Data Direction Bit
For More Information On This Product,
1 = Corresponding port H pin configured as output
0 = Corresponding port H pin configured as input
0
1
shows the port H I/O logic.
READ DDRH ($000F)
WRITE DDRH ($000F)
WRITE PORTH ($000B)
READ PORTH ($000B)
Go to: www.freescale.com
Table 9. Port H Pin Operation
I/O Ports
Figure 25. Port H I/O Circuit
RESET
Input, high-impedance
I/O Pin Mode
Output
Table 9
DDRHx
PHx
summarizes the operation of
Read
Latch
Access to Data Bit
Pin
MOTOROLA
Latch
Write
Latch
22-ports_a
(1)
PHx

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