MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 314

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
IRQ
IRQ1 Pin
MC68HC708XL36
314
NOTE:
When an interrupt pin is edge-triggered only, the CPU interrupt request
remains latched until a vector fetch, software clear, or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the
CPU interrupt request remains latched until both of the following occur:
The vector fetch or software clear can occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the CPU interrupt request
remains pending. A reset clears the CPU interrupt request and the
MODEx control bit even if the pin stays low.
When set, the IMASK1 and IMASK2 bits in the ISCR mask all external
interrupt requests. A latched CPU interrupt request is not presented to
the interrupt priority logic unless the corresponding IMASK bit is clear.
The interrupt mask (I) in the condition code register (CCR) masks all
CPU interrupt requests, including external interrupt requests.
A logic 0 on the IRQ1 pin can latch a CPU interrupt request. A vector
fetch, software clear, or reset clears the IRQ1 CPU interrupt request.
If the MODE1 bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE1 set, both of the following actions must
occur to clear the IRQ1 CPU interrupt request:
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Vector fetch or software clear
Return of the interrupt pin to logic 1
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the CPU interrupt
request. Software can generate the interrupt acknowledge signal
by writing a logic 1 to the ACK1 bit in the interrupt status and
control register (ISCR). The ACK1 bit is useful in applications that
poll the IRQ1 pin and require software to clear the IRQ1 CPU
interrupt request. Writing to the ACK1 bit before leaving an
interrupt service routine can also prevent spurious interrupts due
to noise. Setting ACK1 does not affect subsequent transitions on
the IRQ1 pin. A falling edge that occurs after writing to the ACK1
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IRQ
MOTOROLA
4-intirq2_a

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