MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 316

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
IRQ
IRQ2 Pin
MC68HC708XL36
316
A logic 0 on the IRQ2 pin can latch a CPU interrupt request. A vector
fetch, software clear, or reset clears the IRQ2 CPU interrupt request.
If the MODE2 bit is set, the IRQ2 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE2 set, both of the following actions must
occur to clear an IRQ2 CPU interrupt request:
The vector fetch, software clear, or reset and the return of the IRQ2 pin
to logic 1 can occur in any order. A reset clears the CPU interrupt request
and the MODE2 bit, clearing the CPU interrupt request even if the pin
stays low.
If the MODE2 bit is clear, the IRQ2 pin is falling-edge-sensitive only.
With MODE2 clear, a vector fetch or software clear immediately clears
the IRQ2 CPU interrupt request.
The IRQF2 bit in the ISCR register can be used to check for pending
CPU interrupts. The IRQF2 bit is not affected by the IMASK2 bit, which
makes it useful in applications where polling is preferred.
Freescale Semiconductor, Inc.
For More Information On This Product,
Vector fetch, software clear, or reset — A vector fetch generates
an interrupt acknowledge signal to clear the CPU interrupt
request. Software can generate the interrupt acknowledge signal
by writing a logic 1 to the ACK2 bit in the interrupt status and
control register (ISCR). The ACK2 bit is useful in applications that
poll the IRQ2 pin and require software to clear the IRQ2 CPU
interrupt request. Writing to the ACK2 bit before leaving an
interrupt service routine can also prevent spurious CPU interrupts
due to noise. Setting ACK2 does not affect subsequent transitions
on the IRQ2 pin. A falling edge that occurs after writing to the
ACK2 bit latches another CPU interrupt request. If the IRQ2 mask
bit, IMASK2, is clear, the CPU loads the program counter with the
vector address at locations $FFE0 and $FFE1.
Return of the IRQ2 pin to logic 1 — As long as the IRQ2 pin is at
logic 0, the IRQ2 CPU interrupt request remains latched.
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IRQ
MOTOROLA
6-intirq2_a

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