MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 66

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Resets and Interrupts
SWI Instruction
Break Interrupt
IRQ1 Pin
CGM
DMA
MC68HC708XL36
66
NOTE:
The software interrupt instruction (SWI) causes a nonmaskable
interrupt.
A software interrupt pushes PC onto the stack. An SWI does not push
PC – 1, as a hardware interrupt does.
The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.
A logic 0 on the IRQ1 pin latches an external interrupt request.
The CGM can generate a CPU interrupt request every time the
phase-locked loop circuit (PLL) enters or leaves the locked state. When
the LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.
The DMA module can generate a CPU interrupt request when a channel
x CPU interrupt flag (IFCx) becomes set.
The IFCx bit is the DMA status and control register. The IECx bit is in
DMA control register 1.
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
IFCx is set at the end of a DMA block transfer. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
IFCx is set at the end of a DMA transfer loop. The channel x CPU
interrupt enable bit, IECx, enables DMA channel x CPU interrupt
requests.
Go to: www.freescale.com
Resets and Interrupts
MOTOROLA
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