MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 69

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MC68HC708XL36

Manufacturer Part Number
MC68HC708XL36
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
IRQ2 Pin
KB0–KB7 Pins
13-ri24_e
MOTOROLA
A logic 0 on the IRQ2 pin latches an external interrupt request.
A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
Freescale Semiconductor, Inc.
For More Information On This Product,
Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
Parity error bit (PE) — PE is set when the SCI detects a parity
error in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
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Resets and Interrupts
Resets and Interrupts
MC68HC708XL36
Interrupts
69

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