MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 114

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MC68HC711D3CFB2

Manufacturer Part Number
MC68HC711D3CFB2
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Electrical Characteristics
9.7 Peripheral Port Timing
114
Frequency of operation (E-clock frequency)
E-clock period
Peripheral data setup time
Peripheral data hold time
MCU read of ports A, B, C, and D
Delay time, peripheral data write
1. V
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
MCU read of ports A, B, C, and D
MCU write to port A
MCU writes to ports B, C, and D
t
otherwise noted.
PWD
DD
= 5.0 Vdc ± 10%, V
= 1/4 t
A, B, C, D
PORT A
PORTS
B, C, D
PORTS
cyc
E
E
Characteristic
+ 150 ns
(2)
(2)
SS
= 0 Vdc, T
(1)
PREVIOUS PORT DATA
Figure 9-8. Port Write Timing Diagram
Figure 9-9. Port Read Timing Diagram
A
= T
MC68HC711D3 Data Sheet, Rev. 2.1
L
MCU WRITE TO PORT
PREVIOUS PORT DATA
to T
MCU READ OF PORT
H
. All timing is shown with respect to 20% V
Symbol
t
t
t
PDSU
t
PWD
CYC
PDH
f
O
t PWD
1000
Min
100
1.0
50
1.0 MHz
t PDSU
Max
200
350
1.0
Min
500
100
NEW DATA VALID
t PWD
2.0
t PDH
50
2.0 MHz
Max
200
225
2.0
DD
NEW DATA VALID
and 70% V
Freescale Semiconductor
Min
333
100
3.0
50
3.0 MHz
DD
Max
200
183
, unless
3.0
MHz
Unit
ns
ns
ns
ns

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