MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 39

no-image

MC68HC711D3CFB2

Manufacturer Part Number
MC68HC711D3CFB2
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
3.5.3 Extended
In the extended addressing mode, the effective address of the argument is contained in two bytes
following the opcode byte. These are 3-byte instructions (or 4-byte instructions if a prebyte is required).
One or two bytes are needed for the opcode and two for the effective address.
3.5.4 Indexed
In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value
contained in an index register (IX or IY). The sum is the effective address. This addressing mode allows
referencing any memory location in the 64-Kbyte address space. These are 2- to 5-byte instructions,
depending on whether a prebyte is required.
3.5.5 Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in
the opcode. Operations that use only the index registers or accumulators, as well as control instructions
with no arguments, are included in this addressing mode. These are 1- or 2-byte instructions.
3.5.6 Relative
The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit
signed offset included in the instruction is added to the contents of the program counter to form the
effective branch address. Otherwise, control proceeds to the next instruction. These are usually 2-byte
instructions.
3.6 Instruction Set
Refer to
instruction, the table shows the operand construction, the number of machine code bytes, and execution
time in CPU E-clock cycles.
Freescale Semiconductor
ADCA (opr)
ADCB (opr)
ADDA (opr)
Mnemonic
ABA
ABX
ABY
Table
Add Memory to
Add with Carry
Add with Carry
Accumulators
Operation
Add B to X
Add B to Y
3-2, which shows all the M68HC11 instructions in all possible addressing modes. For each
Add
to A
to B
A
IX + (00 : B) ⇒ IX
IY + (00 : B) ⇒ IY
A + M + C ⇒ A
B + M + C ⇒ B
Description
A + M ⇒ A
A + B ⇒ A
Table 3-2. Instruction Set (Sheet 1 of 8)
MC68HC711D3 Data Sheet, Rev. 2.1
A
A
A
A
A
B
B
B
B
B
A
A
A
A
A
Addressing
Mode
INH
INH
INH
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
18
18
18
18
Opcode
1B
3A
3A
89
99
A9
A9
C9
D9
E9
E9
8B
9B
AB
AB
B9
F9
BB
Instruction
ii
dd
hh
ff
ff
ii
dd
hh
ff
ff
ii
dd
hh
ff
ff
Operand
ll
ll
ll
Cycles
2
3
4
2
3
4
4
5
2
3
4
4
5
2
3
4
4
5
S
X
H
Condition Codes
I
N
Instruction Set
Z
V
C
39

Related parts for MC68HC711D3CFB2