MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 50

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MC68HC711D3CFB2

Manufacturer Part Number
MC68HC711D3CFB2
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Resets, Interrupts, and Low-Power Modes
Table 4-2
condition code and control bits that mask each interrupt.
50
provides a list of the interrupts with a vector location in memory for each, as well as the actual
$FFDC, $FFDD
$FFDA, $FFDB
$FFDE, $FFDF
$FFEC, $FFED
$FFC0, $FFC1
$FFD4, $FFD5
$FFD6, $FFD7
$FFD8, $FFD9
$FFEA, $FFEB
$FFEE, $FFEF
$FFFC, $FFFD
$FFE0, $FFE1
$FFE2, $FFE3
$FFE4, $FFE5
$FFE6, $FFE7
$FFE8, $FFE9
$FFFA, $FFFB
$FFFE, $FFFF
$FFF0, $FFF1
$FFF2, $FFF3
$FFF4, $FFF5
$FFF6, $FFF7
$FFF8, $FFF9
Address
Vector
Table 4-2. Interrupt and Reset Vector Assignments
Reserved
SCI serial system:
SPI serial transfer complete
Pulse accumulator input edge
Pulse accumulator overflow
Timer overflow
Timer input capture 4/output compare 5
Timer output compare 4
Timer output compare 3
Timer output compare 2
Timer output compare 1
Timer input capture 3
Timer input capture 2
Timer input capture 1
Real time interrupt
IRQ (external pin)
XIRQ pin (pseudo non-maskable)
Software interrupt
Illegal opcode trap
COP failure (reset)
Clock monitor fail (reset)
RESET
• SCI transmit complete
• SCI transmit data register empty
• SCI idle line detect
• SCI receiver overrun
• SCI receive data register full
MC68HC711D3 Data Sheet, Rev. 2.1
Interrupt Source
Figure 4-3
shows the interrupt stacking order.
Mask
None
None
None
None
None
CCR
X bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
I bit
NOCOP
Freescale Semiconductor
PAOVI
Local
I4/O5I
Mask
None
None
None
None
None
TCIE
SPIE
OC4I
OC3I
OC2I
OC1I
CME
IC3I
IC2I
IC1I
RTII
ILIE
PAII
TIE
RIE
RIE
TOI

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