MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 64

• Manufacturer Part Number: MC68HC711D3CFB2
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

5.5 Port D
Port D is an 8-bit, general-purpose I/O port with a data register (PORTD) and a data direction register
(DDRD). The eight port D bits (D7–D0) can be used for general-purpose I/O, for the serial
communications interface (SCI) and serial peripheral interface (SPI) subsystems, or for bus data direction
control
5.5.1 Port D Data Register
PORTD can be read at any time and inputs return the sensed levels at the pin; whereas, outputs return
the input level of the port D pin drivers. If PORTD is written, the data is stored in an internal latch, and can
be driven only if port D is configured as general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow on the bus in
expanded and special test modes.
5.5.2 Port D Data Direction Register
DDD7–DDD0 — Data Direction for Port D
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Input/Output (I/O) Ports
When port D is a general-purpose I/O port, the DDRD register controls the direction of the I/O pins as
follows:
In expanded and test modes, bits 6 and 7 are dedicated AS and R/W.
When port D is functioning with the SPI system enabled, bit 5 is dedicated as the slave select (SS)
input. In SPI slave mode, DDD5 has no meaning or effect. In SPI master mode, DDD5 affects port D
bit 5 as follows:
If the SPI is enabled and expects port D bits 2, 3, and 4 (MISO, MOSI, and SCK) to be inputs, then
they are inputs, regardless of the state of DDRD bits 2, 3, and 4. If the SPI expects port D bits 2, 3,
and 4 to be outputs, they are outputs only if DDRD bits 2, 3, and 4 are set.
0 = Configures the corresponding port D pin for input only
1 = Configures the corresponding port D pin for output
0 = Port D bit 5 is an error-detect input to the SPI.
1 = Port D bit 5 is configured as a general-purpose output line.
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
$0008
$0009
DDD7
Bit 7
PD7
Bit 7
Figure 5-8. Data Direction Register for Port D (DDRD)
0
0
Figure 5-7. Port D Data Register (PORTD)
DDD6
PD6
6
0
6
0
MC68HC711D3 Data Sheet, Rev. 2.1
DDD5
PD5
5
0
5
0
DDD4
PD4
4
0
4
0
DDD3
PD3
3
0
3
0
DDD2
PD2
2
0
2
0
DDD1
PD1
1
0
1
0
Freescale Semiconductor
DDD0
Bit 0
PD0
Bit 0
0
0