MC68HC711D3CFB2 FREESCALE [Freescale Semiconductor, Inc], MC68HC711D3CFB2 Datasheet - Page 88

• Manufacturer Part Number: MC68HC711D3CFB2
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Programmable Timer
The control and status bits that implement the input capture functions are contained in the PACTL,
TCTL2, TMSK1, and TFLG1 registers.
To configure port A bit 3 as an input capture, clear the DDRA3 bit of the PACTL register. Note that this bit
is cleared out of reset. To enable PA3 as the fourth input capture, set the I4/O5 bit in the PACTL register.
Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the
DDRA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on
the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4.
88
CLOCK
MCU E
TI4/O5 (HI)
TOC2 (HI)
TOC3 (HI)
TOC4 (HI)
TOC1 (HI)
TIC1 (HI)
TIC2 (HI)
TIC3 (HI)
16-BIT COMPARATOR =
16-BIT COMPARATOR =
16-BIT COMPARATOR =
16-BIT COMPARATOR =
16-BIT COMPARATOR =
16-BIT LATCH
16-BIT LATCH
16-BIT LATCH
16-BIT LATCH
PRESCALER — DIVIDE BY
16-BIT TIMER BUS
PR1
1, 4, 8, 16
TI4/O5 (LO)
TOC2 (LO)
TOC3 (LO)
TOC4 (LO)
TOC1 (LO)
TIC2 (LO)
TIC3 (LO)
TIC1 (LO)
PR0
CLK
CLK
CLK
CLK
Figure 8-2. Capture/Compare Block Diagram
I4/O5
TCNT (HI)
MC68HC711D3 Data Sheet, Rev. 2.1
16-BIT FREE RUNNING
IC4
STATUS
OC5
TFLG 1
FLAGS
I4/O5F
OC1F
OC2F
OC3F
OC4F
IC1F
IC2F
IC3F
COUNTER
TCNT (LO)
COMPARE
AND PULSE ACCUMULATOR
OUTPUT
FORCE
CFORC
FOC1
FOC2
FOC3
FOC4
FOC5
COP WATCHDOG,
TAPS FOR RTL,
INTERRUPT
ENABLES
TMSK 1
TOF
I4/O5I
TOI
OC1I
OC2I
OC3I
OC4I
IC1I
IC2I
IC3I
INTERRUPT REQUESTS
(FURTHER QUALIFIED
BY I BIT IN CCR)
3
2
1
8
7
6
5
4
9
ACCUMULATOR
CONTROL
TO PULSE
PORT A
Freescale Semiconductor
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PIN
PORT A
PA7/OC1/
PA6/OC2/
PA5/OC3/
PA4/OC4/
OC5/OC1
PA2/IC1
PA1/IC2
PA0/IC3
PA3/IC4/
PINS
OC1
OC1
OC1
PAI