LAN83C185_03 SMSC [SMSC Corporation], LAN83C185_03 Datasheet
LAN83C185_03
Related parts for LAN83C185_03
LAN83C185_03 Summary of contents
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Product Features Single Chip Ethernet Phy ■ Fully compliant with IEEE 802.3/802.3u standards ■ 10BASE-T and 100BASE-TX support ■ Supports Auto-negotiation and Parallel Detection ■ Automatic Polarity Correction ■ Integrated DSP with Adaptive Equalizer ■ Baseline Wander (BLW) Correction ■ ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2003 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems and SMSC are registered trademarks of Standard Microsystems Corporation. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table of Contents Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 5.4.1 Carrier Sense . . . . . . . . . . . . . . . . . . . . . . . . . ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet List of Figures Figure 1.1 LAN83C185 Architectural Overview ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Rev. 0.6 (12-12-03) vi DATASHEET Datasheet SMSC LAN83C185 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet List of Tables Table 2.1 LAN83C185 64-PIN TQFP Pinout . . . . . . . . . . . . . . . . . . ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 5.43 Register 18 - Special Modes . . . . . . . . . . . . . . . . . . . . . ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 1 General Description The SMSC LAN83C185 is a low-power, highly integrated analog interface IC for high-performance embedded Ethernet applications. The LAN83C185 requires only a single +3.3V ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Rev. 0.6 (12-12-03) 2 DATASHEET Datasheet SMSC LAN83C185 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 2 Pin Configuration 64 63 GPO0/MII 1 GPO1/PHYAD4 2 GPO2 3 MODE0 4 MODE1 5 MODE2 6 VSS1 7 VDD1 8 TEST0 9 TEST1 10 CLK_FREQ ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 2.1 LAN83C185 64-PIN TQFP Pinout PIN NO. PIN NAME 1 GPO0/MII 2 GPO1/PHYAD4 3 GPO2 4 MODE0 5 MODE1 6 MODE2 7 VSS1 8 VDD1 9 TEST0 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 3 Pin Description This chapter describes in detail the functionality of each of the five main architectural blocks. The term “block” defines a stand-alone entity on ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) PIN NO. SIGNAL NAME 37 TX_ER (TXD4) 48 CRS 33 RX_DV 30 RXD2 29 RXD3 38 TX_CLK 34 RX_CLK PIN NO. SIGNAL NAME 16 SPEED100 17 LINKON 19 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet PIN NO. SIGNAL NAME 2 PHYAD4 20 PHYAD3 19 PHYAD2 17 PHYAD1 16 PHYAD0 6 MODE2 5 MODE1 4 MODE0 10 TEST1 9 TEST0 12 REG_EN PIN ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 3.5 General Signals (continued) PIN NO. SIGNAL NAME 1 GPO0 PIN NO. SIGNAL NAME 51 TXP 50 TXN 55 RXP 54 RXN PIN NO. SIGNAL NAME 59 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet PIN NO. SIGNAL NAME 60 AVSS4 62 AVSS5 13 VREG 14 VDD_CORE 8 VDD1 18 VDD2 43 VDD3 7 VSS1 15 VSS2 21 VSS3 24 VSS4 28 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Rev. 0.6 (12-12-03) 10 DATASHEET Datasheet SMSC LAN83C185 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 4 Architecture Details 4.1 Top Level Functional Architecture Functionally, the PHY can be divided into the following sections: 100Base-TX transmit and receive ■ 10Base-T transmit and ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) The encoding process may be bypassed by clearing bit 6 of register 31. When the encoding is th bypassed the 5 transmit data bit is equivalent to TX_ER. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 4.1 4B/5B Code Table (continued) CODE GROUP SYM 00010 V INVALID, RX_ER if during RX_DV 00011 V INVALID, RX_ER if during RX_DV 00101 V INVALID, RX_ER ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) RX_CLK MAC MII 25MHz by 4 bits MLT-3 NRZI NRZI Converter Converter A/D Magnetics MLT-3 Converter 4.3 100Base-TX Receive The receive data path is shown in 4.3.1 100M ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.3.4 Descrambling The descrambler performs an inverse function to the scrambler in the transmitter and also performs the Serial In Parallel Out (SIPO) conversion of the data. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 4.3.8 Receiver Errors During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0 through F), and the /T/R/ (ESD) symbol pair. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 4.5 10Base-T Receive The 10Base-T receiver gets the Manchester- encoded analog signal from the cable via the magnetics. It recovers the receive clock from the signal and ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 4.6.1 MII The MII includes 16 interface signals: transmit data - TXD[3:0] ■ transmit strobe - TX_EN ■ transmit clock - TX_CLK ■ transmit error - TX_ER/TXD4 ■ ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Power-down reset ■ Link status down ■ Setting register 0, bit 9 high (auto-negotiation restart) ■ On detection of one of these events, the PHY begins auto-negotiation ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 4.7.2 Re-starting Auto-negotiation Auto-negotiation can be re-started at any time by setting register 0, bit 9. Auto-negotiation will also re- start if the link is broken at any ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet The minimum cycle time (time between two consecutive rising or two consecutive falling edges) is 400 ns. These modest timing requirements allow this interface to be easily ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Rev. 0.6 (12-12-03) 22 DATASHEET Datasheet SMSC LAN83C185 ...
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Chapter 5 Registers Reset Loopback Speed Select A/N Enable 100Base- 100Base- 100Base- 10Base Full Full Duplex Half Duplex Duplex ...
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Table 5.6 Auto-Negotiation Link Partner Base Page Ability Register: Register 5 (Extended Next Acknowledge Remote Reserved Page Fault Table 5.7 Auto-Negotiation Expansion Register: Register 6 (Extended Reserved Table 5.8 ...
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Table 5.11 Register 10 (Extended ...
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Table 5.17 Silicon Revision Register 16: Vendor-Specific Reserved Table 5.18 Mode Control/ Status Register 17: Vendor-Specific Reserved FASTRIP EDPWRDOWN Reserved LOWSQEN MIIMODE CLKSELFREQ DSPBP ...
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Table 5.22 TSTREAD2 Register 21: Vendor-Specific ...
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Table 5.28 Special Control/Status Indications Register 27: Vendor-Specific Reserved SWRST_FAST SQEOFF Table 5.29 Special Internal Testability Control Register 28: Vendor-Specific Table 5.30 Interrupt Source Flags Register 29: Vendor-Specific 15 14 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.1 SMI Register Mapping The following registers are supported (register numbers are in decimal): REGISTER # 0 Basic Control Register 1 Basic Status Register 2 PHY Identifier ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) ADDRESS NAME 0.15 Reset 1 = software reset. Bit is self-clearing. For best results, 0.14 Loopback 1 = loopback mode normal operation 0.13 Speed Select 1 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.35 Register 1 - Basic Status (continued) ADDRESS NAME 1.3 Auto-Negotiate Ability 1.2 Link Status 1.1 Jabber Detect 1.0 Extended Capabilities Table 5.36 Register 2 - ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 5.38 Register 4 - Auto Negotiation Advertisement (continued) ADDRESS NAME 4.8 100Base-TX Full Duplex 4.7 100Base-TX 4.6 10Base-T Full Duplex 4.5 10Base-T 4.4:0 Selector Field Table 5.39 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.40 Register 6 - Auto Negotiation Expansion ADDRESS NAME 6.15:5 Reserved 6.4 Parallel Detection Fault 6.3 Link Partner Next Page Able 6.2 Next Page Able 6.1 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 5.42 Register 17 - Mode Control/Status (continued) ADDRESS NAME 17.8 FASTEST 17.7:5 Reserved 17.4 Reserved 17.3 PHYADBP 17.2 Force Good Link Status 17.1 ENERGYON 17.0 Reserved Table ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.43 Register 18 - Special Modes (continued) ADDRESS NAME 18.4:0 PHYAD ADDRESS NAME 20.15 READ 20.14 WRITE 20.13:11 Reserved 20.10 TEST MODE 20.9:5 READ ADDRESS 20.4:0 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) ADDRESS NAME 23.15:0 WRITE_DATA Table 5.48 Register 27 - Special Control/Status Indications ADDRESS NAME 27.15:13 Reserved 27.12 SWRST_FAST 27:11 SQEOFF 27:10 VCOOFF_LP 27.9 Reserved 27.8 Reserved 27.7 Reserved ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 5.50 Register 29 - Interrupt Source Flags (continued) ADDRESS NAME 29.6 INT6 29.5 INT5 29.4 INT4 29.3 INT3 29.2 INT2 29.1 INT1 29.0 Reserved Table 5.51 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 5.52 Register 31 - PHY Special Control/Status (continued) ADDRESS NAME 31.4:2 Speed Indication 31.1 Reserved 31.0 Scramble Disable 5.3 Management Interrupt The Management interface supports an interrupt ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.4.2 Collision Detect A collision is the occurrence of simultaneous transmit and receive operations. The COL output is asserted to indicate that a collision has been detected. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) the PHY powers-up. It automatically resets itself into the state it had prior to power-down, and asserts the nINT interrupt if the ENERGYON interrupt is enabled. to activate ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Phy Address = 1 LED output = active low VDD Figure 5.1 PHY Address Strapping on LEDS The ACTIVITY LED output is driven active when CRS is ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 5.4.9.2 Mode Bus – MODE[2:0] The MODE[2:0] bus controls the configuration of the 10/100 digital block. MODE[2:0] MODE DEFINITIONS 000 10Base-T Half Duplex. Auto-negotiation disabled. 001 10Base-T Full ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.5.1.2 General Characteristics ITEM Full Scale Input voltage Input Common Mode 5.5.2 100M PLL Three main functions are included in the 100M PLL: a clock multiplier to ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 5.5.6.1 Functional Description The Data recovery PLL has two modes of operation: Frequency Mode and Data Mode. In frequency mode, the VCO locks to the external reference clock. ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 5.6 DSP Block 5.6.1 General Description The “DSP Block” includes the following modules: DSP Core (Equalizer, Timing and BLW correction), Testability / Configuration module (Testability / Configuration ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Rev. 0.6 (12-12-03) 46 DATASHEET Datasheet SMSC LAN83C185 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 6 Electrical Characteristics The timing diagrams and limits in this section define the requirements placed on the external signals of the Phy. 6.1 Serial Management Interface ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 6.2 100Base-TX Timings 6.2.1 100M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER PARAMETER DESCRIPTION T2.1 Receive signals setup to RX_CLK rising T2.2 Receive signals hold from RX_CLK rising ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.3 10Base-T Timings 6.3.1 10M MII Receive Timing RX_CLK RXD[3:0] RX_DV RX_ER PARAMETER DESCRIPTION T4.1 Receive signals setup to RX_CLK rising T4.2 Receive signals hold from RX_CLK ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 6.4 Reset Timing nRST Configuration signals Output drive PARAMETER DESCRIPTION T6.1 Reset Pulse Width T6.2 Configuration input setup to nRST rising T6.3 Configuration input hold after nRST rising ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 6.1 Power Consumption Device Only Total Power Mode (mW) 10BASE-T /w traffic 88 Idle 86 Energy Detect Power Down 48 AN General Power Down 48 Non-AN ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) 6.5.2.2 Power Consumption Device and System Components Power measurements taken under the following conditions: +25 ° C Temperature: Device VDD: +3.30 V Table 6.2 Power Consumption Device and ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet 6.5.3 DC Characteristics - Input and Output Buffers Table 6.3 MII BUS INTERFACE SIGNALS PIN NO. NAME BUFFER TYPE 41 TXD0 42 TXD1 44 TXD2 45 TXD3 ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) BUFFER PIN NO. NAME TYPE 51 TXP AO 50 TXN AO 55 RXP 54 RXN PIN NO. NAME BUFFER TYPE 16 SPEED100 17 LINKON 19 ACTIVITY 20 FDUPLEX ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Table 6.6 Configuration Inputs (continued) PIN NO. NAME BUFFER TYPE 12 REG_EN 1 MII PIN NO. NAME BUFFER TYPE 1 GPO0 2 GPO1 3 GPO2 46 nINT ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Table 6.9 Internal Pull-Up / Pull-/Down Configurations (continued) PIN NO. NAME 16 SPEED100 17 LINKON 19 ACTIVITY 20 FDUPLEX 46 nINT Table 6.10 100Base-TX Transceiver Characteristics PARAMETER Peak ...
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High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY) Datasheet Chapter 7 Package Outline Figure 7.1 64 Pin TQFP Package Outline, 10X10X1.4 Body Footprint Table 7.1 64 Pin TQFP Package Parameters MIN NOMINAL A ~ ...