MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 100

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Resets and Interrupts
5.5.1 Interrupt Recognition and Register Stacking
5.5.2 Non-Maskable Interrupt Request (XIRQ)
Data Sheet
100
An interrupt can be recognized at any time after it is enabled by its local mask, if
any, and by the global mask bit in the CCR. Once an interrupt source is recognized,
the CPU responds at the completion of the instruction being executed. Interrupt
latency varies according to the number of cycles required to complete the current
instruction. When the CPU begins to service an interrupt, the contents of the CPU
registers are pushed onto the stack in the order shown in
value is stacked, the I bit and the X bit, if XIRQ is pending, are set to inhibit further
interrupts. The interrupt vector for the highest priority pending source is fetched
and execution continues at the address specified by the vector. At the end of the
interrupt service routine, the return-from-interrupt instruction is executed and the
saved registers are pulled from the stack in reverse order so that normal program
execution can resume. Refer to
Non-maskable interrupts are useful because they can always interrupt CPU
operations. The most common use for such an interrupt is for serious system
problems, such as program runaway or power failure. The XIRQ input is an
updated version of the NMI (non-maskable interrupt) input of earlier MCUs.
Upon reset, both the X bit and I bit of the CCR are set to inhibit all maskable
interrupts and XIRQ. After minimum system initialization, software can clear the X
bit by a TAP instruction, enabling XIRQ interrupts. Thereafter, software cannot set
the X bit. Thus, an XIRQ interrupt is a non-maskable interrupt. Because the
operation of the I-bit-related interrupt structure has no effect on the X bit, the
internal XIRQ pin remains unmasked. In the interrupt priority logic, the XIRQ
interrupt has a higher priority than any source that is maskable by the I bit. All
I-bit-related interrupts operate normally with their own priority relationship.
When an I-bit-related interrupt occurs, the I bit is automatically set by hardware
after stacking the CCR byte. The X bit is not affected. When an X-bit-related
interrupt occurs, both the X and I bits are automatically set by hardware after
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5-5. Stacking Order on Entry to Interrupts
Go to: www.freescale.com
Memory Location
Resets and Interrupts
SP–1
SP–2
SP–3
SP–4
SP–5
SP–6
SP–7
SP–8
SP
Section 4. Central Processor Unit
CPU Registers
ACCA
ACCB
CCR
PCH
PCL
IYH
IXH
IYL
IXL
Table
M68HC11E Family — Rev. 5
5-5. After the CCR
(CPU).
MOTOROLA