MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 118

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MC68HC711E20CFS2

Manufacturer Part Number
MC68HC711E20CFS2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
Serial Communications Interface (SCI)
Data Sheet
118
Note: Refer to
REQUESTS
TRANSMITTER
BAUD RATE
SCI Rx
CLOCK
Figure B-1. EVBU Schematic Diagram
SCCR1 SCI CONTROL 1
SCI INTERRUPT
REQUEST
serial shift register. The output of the serial shift register is applied to TxD as long
as transmission is in progress or the transmit enable (TE) bit of serial
communication control register 2 (SCCR2) is set. The block diagram,
shows the transmit serial shift register and the buffer logic at the top of the figure.
H (8) 7 6 5 4 3 2 1 0 L
10 (11) - BIT Tx SHIFT REGISTER
Freescale Semiconductor, Inc.
Figure 7-1. SCI Transmitter Block Diagram
SCDR Tx BUFFER
For More Information On This Product,
Serial Communications Interface (SCI)
TDRE
TIE
TC
TCIE
Go to: www.freescale.com
CONTROL LOGIC
TRANSMITTER
SCSR INTERRUPT STATUS
for an example of connecting TxD to a PC.
WRITE ONLY
SCCR2 SCI CONTROL 2
DIRECTION (OUT)
FORCE PIN
8
AND CONTROL
PIN BUFFER
DDD1
8
INTERNAL
DATA BUS
8
M68HC11E Family — Rev. 5
PD1
TxD
Figure
SEE NOTE
MOTOROLA
7-1,

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