MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 153

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.4.6 Timer Control Register 1
M68HC11E Family — Rev. 5
MOTOROLA
next CPU cycle so that a double-byte read returns the full 16-bit state of the counter
at the time of the MSB read cycle.
The bits of this register specify the action taken as a result of a successful OCx
compare.
OM[2:5] — Output Mode Bits
OL[2:5] — Output Level Bits
Register name: Timer Counter Register (High)
Register name: Timer Counter Register (Low)
These control bit pairs are encoded to specify the action taken after a successful
OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear.
Refer to
Address:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 9-3
$1020
Bit 15
OM2
Bit 7
Bit 7
Bit 7
Bit 7
OMx
0
0
0
0
0
1
1
Figure 9-16. Timer Control Register 1 (TCTL1)
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Figure 9-15. Timer Counter Register (TCNT)
Table 9-3. Timer Output Compare Actions
= Unimplemented
OLx
Bit 14
Bit 6
OL2
0
1
0
1
for the coding.
6
0
6
0
6
0
Timing System
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to 0
Set OCx output line to 1
Bit 13
OM3
Bit 5
5
0
5
0
5
0
Action Taken on Successful Compare
Address: $100F
Address: $100E
Bit 12
Bit 4
OL3
4
0
4
0
4
0
Bit 11
OM4
Bit 3
3
0
3
0
3
0
Bit 10
Bit 2
OL4
2
0
2
0
2
0
OM5
Bit 9
Bit 1
Output Compare
1
0
1
0
1
0
Timing System
Data Sheet
Bit 0
Bit 0
Bit 0
Bit 0
Bit 8
OL5
0
0
0
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