MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 157

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.5.1 Timer Interrupt Mask Register 2
M68HC11E Family — Rev. 5
MOTOROLA
NOTE:
The clock source for the RTI function is a free-running clock that cannot be stopped
or interrupted except by reset. This clock causes the time between successive RTI
timeouts to be a constant that is independent of the software latencies associated
with flag clearing and service. For this reason, an RTI period starts from the
previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt
request is generated. After reset, one entire RTI period elapses before the RTIF
is set for the first time. Refer to the
9.5.2 Timer Interrupt Flag Register
Register.
This register contains the real-time interrupt enable bits.
TOI — Timer Overflow Interrupt Enable Bit
RTII — Real-Time Interrupt Enable Bit
PAOVI — Pulse Accumulator Overflow Interrupt Enable Bit
PAII — Pulse Accumulator Input Edge Bit
Bits [3:2] — Unimplemented
PR[1:0] — Timer Prescaler Select Bits
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Bits in TMSK2 enable
the corresponding interrupt sources.
Refer to
Refer to
Always read 0
Refer to
Address:
Reset:
Read:
Write:
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to 1
0 = RTIF interrupts disabled
1 = Interrupt requested when RTIF set to 1
Freescale Semiconductor, Inc.
For More Information On This Product,
9.7 Pulse
9.7 Pulse
Table
$1024
Figure 9-21. Timer Interrupt Mask 2 Register (TMSK2)
Bit 7
TOI
0
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9-4.
= Unimplemented
RTI
Accumulator.
Accumulator.
6
0
Timing System
PAOVI
5
0
9.4.9 Timer Interrupt Mask 2
2, and
PAII
4
0
9.5.3 Pulse Accumulator Control
3
0
2
0
Real-Time Interrupt (RTI)
Register,
PR1
1
0
Timing System
Data Sheet
Bit 0
PR0
0
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