MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 161

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

9.7.1 Pulse Accumulator Control Register
M68HC11E Family — Rev. 5
MOTOROLA
Pulse accumulator control bits are also located within two timer registers, TMSK2
and TFLG2, as described in the following paragraphs.
Four of this register’s bits control an 8-bit pulse accumulator system. Another bit
enables either the OC5 function or the IC4 function, while two other bits select the
rate for the real-time interrupt system.
DDRA7 — Data Direction for Port A Bit 7
PAEN — Pulse Accumulator System Enable Bit
PAMOD — Pulse Accumulator Mode Bit
PEDGE — Pulse Accumulator Edge Control Bit
Refer to
This bit has different meanings depending on the state of the PAMOD bit, as
shown in
Address:
Reset:
Read:
Write:
Frequency
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = Event counter
1 = Gated time accumulation
12.0 MHz
Freescale Semiconductor, Inc.
4.0 MHz
8.0 MHz
Crystal
For More Information On This Product,
Figure 9-25. Pulse Accumulator Control Register (PACTL)
DDRA7
Section 6. Parallel Input/Output (I/O)
$1026
Table
PAMOD
Bit 7
0
0
0
1
1
Go to: www.freescale.com
Table 9-7. Pulse Accumulator Edge Control
9-7.
PAEN
Table 9-6. Pulse Accumulator Timing
E Clock
6
0
PEDGE
1 MHz
2 MHz
3 MHz
Timing System
0
1
0
1
PAMOD
5
0
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A 0 on PAI inhibits counting.
A 1 on PAI inhibits counting.
Cycle Time
PEDGE
1000 ns
500 ns
333 ns
4
0
Action on Clock
DDRA3
3
0
Ports.
21.33 µs
E ÷ 64
64 µs
32 µs
I4/O5
2
0
Pulse Accumulator
RTR1
16.384 ms
1
0
Overflow
8.192 ms
5.461 ms
Timing System
PACNT
Data Sheet
RTR0
Bit 0
0
161