MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 51

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

2.3.3.3 System Configuration Options Register
M68HC11E Family — Rev. 5
MOTOROLA
REG[3:0] — 64-Byte Register Block Position
The 8-bit, special-purpose system configuration options register (OPTION) sets
internal system configuration options during initialization. The time protected
control bits, IRQE, DLY, and CR[1:0], can be written only once after a reset and
then they become read-only. This minimizes the possibility of any accidental
changes to the system configuration.
1. Can be written only once in first 64 cycles out of reset in normal modes or at any time during
These four bits specify the upper hexadecimal digit of the address for the
64-byte block of internal registers. The register block, positioned at the
beginning of any 4-Kbyte page in the memory map, is initialized to address
$1000 out of reset. Refer to
Address: $1039
special modes.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
Figure 2-13. System Configuration Options Register (OPTION)
RAM[3:0]
Table 2-4. RAM Mapping
For More Information On This Product,
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADPU
Bit 7
Operating Modes and On-Chip Memory
0
Go to: www.freescale.com
= Unimplemented
CSEL
6
0
$C000–$CxFF
$D000–$DxFF
$A000–$AxFF
$B000–$BxFF
$E000–$ExFF
$F000–$FxFF
$0000–$0xFF
$1000–$1xFF
$2000–$2xFF
$3000–$3xFF
$4000–$4xFF
$5000–$5xFF
$6000–$6xFF
$7000–$7xFF
$8000–$8xFF
$9000–$9xFF
Address
IRQE
Table
5
0
(1)
2-5.
DLY
4
1
(1)
Table 2-5. Register Mapping
Operating Modes and On-Chip Memory
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CME
3
0
2
0
$C000–$C03F
$D000–$D03F
$A000–$A03F
$B000–$B03F
$E000–$E03F
$0000–$003F
$1000–$103F
$2000–$203F
$3000–$303F
$4000–$403F
$5000–$503F
$6000–$603F
$7000–$703F
$8000–$803F
$9000–$903F
$F000–$F03F
Address
CR1
1
0
(1)
Memory Map
Data Sheet
CR0
Bit 0
0
(1)
51