MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 77

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

4.2.6 Condition Code Register (CCR)
4.2.6.1 Carry/Borrow (C)
4.2.6.2 Overflow (V)
4.2.6.3 Zero (Z)
4.2.6.4 Negative (N)
4.2.6.5 Interrupt Mask (I)
M68HC11E Family — Rev. 5
MOTOROLA
This 8-bit register contains:
In the M68HC11 CPU, condition codes are updated automatically by most
instructions. For example, load accumulator A (LDAA) and store accumulator A
(STAA) instructions automatically set or clear the N, Z, and V condition code flags.
Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange
instructions do not affect the condition codes. Refer to
what condition codes are affected by a particular instruction.
The C bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during
an arithmetic operation. The C bit also acts as an error flag for multiply and divide
operations. Shift and rotate instructions operate with and through the carry bit to
facilitate multiple-word shift operations.
The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the
V bit is cleared.
The Z bit is set if the result of an arithmetic, logic, or data manipulation operation
is 0. Otherwise, the Z bit is cleared. Compare instructions do an internal implied
subtraction and the condition codes, including Z, reflect the results of that
subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no
other condition flags. For these operations, only = and ≠ conditions can be
determined.
The N bit is set if the result of an arithmetic, logic, or data manipulation operation
is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be negative
if its most significant bit (MSB) is a 1. A quick way to test whether the contents of a
memory location has the MSB set is to load it into an accumulator and then check
the status of the N bit.
The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable
interrupt sources. While the I bit is set, interrupts can become pending, but the
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Five condition code indicators (C, V, Z, N, and H),
Two interrupt masking bits (IRQ and XIRQ)
A stop disable bit (S)
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Table
4-2, which shows
CPU Registers
Data Sheet
77