MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 101

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
7.8.4
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt.
READ:
WRITE:
TDRE — Transmit Data Register Empty Flag
TC — Transmit Complete Flag
RDRF — Receive Data Register Full Flag
IDLE — Idle Line Detected Flag
OR — Overrun Error Flag
Serial Communications Status Register (SCSR)
RESET:
of the break code, the transmitter sends at least one high bit to guarantee recognition of
a valid start bit. If the transmitter is currently empty and idle, setting and clearing SBK is
likely to queue two character times of break because the first break transfers almost
immediately to the shift register and the second is then queued into the parallel transmit
buffer.
Any time (used in auto clearing mechanism).
Has no meaning or effect.
This bit is set when the byte in the transmit data register is transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing
to the transmit data register. Reset sets this bit.
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit
(no data in shifter, no preamble, no break). When TC is set the serial line will go idle
(continuous MARK). Reset sets this bit.
This bit is set when the contents of the receiver serial shift register is transferred to the
receiver data register.
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive “1”s). This bit will not be set by the idle line condition when the RWU bit is
set. Once cleared, IDLE will not be set again until after RDRF has been set, (until after
the line has been active and becomes idle again).
This bit is set when a new byte is ready to be transferred from the receiver shift register
to the receiver data register and the receive data register is already full (RDRF bit is set).
Data transfer is inhibited until this bit is cleared.
$102E
TDRE
7
1
TC
SERIAL COMMUNICATIONS INTERFACE
6
1
RDRF
5
0
IDLE
4
0
OR
3
0
NF
2
0
FE
1
0
0
0
0
SCSR
MOTOROLA
7-11