MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 111

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
8.4.2
READ:
WRITE:
SPIF — SPI Interrupt Request Flag
WCOL — Write Collision
MODF — SPI Mode Error Interrupt Status Flag
8.4.3
READ:
WRITE:
RESET:
The serial peripheral data I/O register is used to transmit and receive data on the serial bus. Only
a write to this register will initiate transmission/reception of another byte, and this will only occur in
Status Register (SPSR)
Data I/O Register (SPDAT)
RESET:
RESET:
Any time.
Has no meaning or effect.
The serial peripheral data transfer flag bit is set after the eighth SCK cycle in a data
transfer and it is cleared by reading the SPSR register (with SPIF set) followed by reading
from or writing to the SPI Data Register (SPDAT).
The write collision bit is used to indicate that a serial transfer was in progress when the
MCU tried to write new data into the SPDAT data register. The MCU write is disabled to
avoid writing over the data being transmitted. No interrupt is generated because the error
status flag can be read upon completion of the transfer that was in progress at the time
of the error. This flag is automatically cleared by a read of the SPSR (with WCOL set)
followed by an access (read or write) to the SPDAT register.
This bit is set automatically by SPI hardware if the MSTR control bit is set to one and the
SS input pin goes low. This condition is not permitted in normal operation. In the special
case where DDRD bit 5 is set to one, the Port D bit 5 pin is a general purpose output pin
rather than being dedicated as the slave select input for the SPI system. In this special
case the mode error function is inhibited and MODF remains at zero. This flag is
automatically cleared by a read of the SPSR (with MODF set) followed by a write to the
SPCR register.
Any time (normally only after SPIF flag set)
Any time (see WCOL write collision flag).
Does not affect this register.
$102A
$1029
BIT7
SPIF
7
0
7
0
WCOL
BIT6
6
0
6
0
SERIAL PERIPHERAL INTERFACE
BIT5
5
0
5
0
0
MODF
BIT4
4
0
4
0
BIT3
3
0
3
0
0
BIT2
2
0
2
0
0
BIT1
1
0
1
0
0
BIT0
0
0
0
0
0
SPDAT
SPSR
MOTOROLA
8-7