MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 126
MC68HC711G5
Manufacturer Part Number
MC68HC711G5
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC711G5.pdf
(195 pages)
- Current page: 126 of 195
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Note:
READ:
WRITE:
RESET:
10.5.4 Clock Select Register (PWCLK)
READ:
WRITE:
RESET:
CON34 — Concatenate channels 3 and 4
MOTOROLA
10-6
RESET:
$106C
$106D
$106E
$106F
If the duty register is greater than or equal to the value in the period register there will be
no duty change in state. In addition, if the duty register is set to $00 the output will always
be in the state which would normally be the state changed to at the duty change of state.
Refer to the “Boundary Cases” section for more information on this.
Any time.
Any time.
$FF.
Any time.
Any time.
$00.
1 – Channels 3 and 4 are concatenated to create one 16-bit PWM channel. (Channel
0 – Channels 3 and 4 are separate 8-bit PWM channels.
$1060
3 becomes the high order byte and channel 4 becomes the low order byte. The
channel 4 output is used as the output for this 16-bit PWM (bit 3 of Port H)).
CON34
BIT7
BIT7
BIT7
BIT7
7
7
0
CON12
BIT6
BIT6
BIT6
BIT6
6
6
0
PULSE WIDTH MODULATION TIMER
BIT5
BIT5
BIT5
BIT5
PCKA2
5
5
0
PCKA1
BIT4
BIT4
BIT4
BIT4
4
4
0
BIT3
BIT3
BIT3
BIT3
3
3
0
0
PCKB3
BIT2
BIT2
BIT2
BIT2
2
2
0
PCKB2
BIT1
BIT1
BIT1
BIT1
1
1
0
PCKB1
BIT0
BIT0
BIT0
BIT0
0
0
0
PWDTY1
PWDTY2
PWDTY3
PWDTY4
PWCLK
MC68HC11G5
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