MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 149

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
11.6.6 Counter Compare Registers (ECMPx)
READ:
WRITE:
RESET:
Compare registers ECMP1A and ECMP1B are associated with counter EVCNT1. Compare
registers ECMP2A and ECMP2B are associated with counter EVCNT2.
The PWM function of the event counter differs from the main PWM (discussed in Section 10) in that
it has no double buffered duty and period registers. This means that it is possible to generate a cycle
in which there is no duty change of state. This occurs when the duty value written is lower than the
previous value, but the counter is already past the new value. In this case the counter register will
increment all the way to the period count, roll over to $00 and count up to the new duty value before
matching. This situation can be avoided by using the event interrupts to help calculate, in software,
the correct values of duty and period to be written to the compare registers.
In mode 0:
ECMP1A and ECMP1B:
ECMP2A and ECMP2B:
In modes 1, 2 and 3:
ECMP1A and ECMP1B:
(These values follow the boundary conditions of the PWM function.)
ECMP2A and ECMP2B:
11.7
11.8
PWM USING THE EVENT COUNTER
EFFECTIVE RANGE OF THE SET UP VALUES
RESET:
$1076
$1077
$1078
$1079
Any time.
Any time.
$FF.
BIT7
BIT7
BIT7
BIT7
7
1
BIT6
BIT6
BIT6
BIT6
6
1
0 to 255 ($00 to $FF)
0 to 255 ($00 to $FF)
1 to 255 ($01 to $FF)
1 to 255 to 256 ($01 to $FF to $00).
BIT5
BIT5
BIT5
BIT5
5
1
EVENT COUNTER
BIT4
BIT4
BIT4
BIT4
4
1
BIT3
BIT3
BIT3
BIT3
3
1
BIT2
BIT2
BIT2
BIT2
2
1
BIT1
BIT1
BIT1
BIT1
1
1
BIT0
BIT0
BIT0
BIT0
0
1
ECMP1A
ECMP2A
ECMP1B
ECMP2B
MOTOROLA
11-19