MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 154

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

12.2.3 Extended Addressing (EXT)
In the extended addressing mode, the effective address of the instruction appears explicitly in the
two bytes following the opcode. Therefore, the length of most instructions using the extended
addressing mode is three bytes: one for the opcode and two for the effective address.
12.2.4 Indexed Addressing (IND, X; IND, Y)
In the indexed addressing mode, either the X or Y index register is used in calculating the effective
address. In this case, the effective address is variable and depends on the current contents of the
X or Y index register and a fixed 8-bit unsigned offset contained in the instruction. This addressing
mode can be used to reference any memory location in the 64 kbyte address space. These are
usually two (or three if a pre-byte is required) byte instructions, the opcode plus the 8-bit offset.
12.2.5 Inherent Addressing (INH)
In the inherent addressing mode, all of the information is contained in the opcode. The operands
(if any) are registers and no memory reference is required. These are usually one or two
byte instructions.
12.2.6 Relative Addressing (REL)
The relative addressing mode is used for branch instructions. If the branch condition is true, the
contents of the 8-bit signed byte following the opcode (the offset) is added to the contents of the
program counter to form the effective branch address; otherwise, control proceeds to the instruction
immediately following the branch instruction. These are usually two byte instructions.
12.3
INSTRUCTION SET
This section explains the basic capabilities and organization of the instruction set. For this
discussion the instruction set is divided into functional groups of instructions. Some instructions will
appear in more than one functional group. For example, transfer accumulator A to condition code
register (TAP) appears in the condition-code-register group and in the load/store/transfer subgroup
of accumulator/memory instructions. For a detailed explanation of each instruction refer to the
M68HC11 Reference Manual (M68HC11RM/D).
In order to expand the number of instructions used in the MC68HC11G5, a pre-byte mechanism has
been added which affects certain instructions. Most of the instructions affected are associated with
the Y index register. Instructions which do not require a pre-byte are said to reside in page 1 of the
opcode map. Instructions requiring a pre-byte are said to reside in pages 2, 3, and 4 of the opcode
map. The opcode map pre-byte codes are $18 for page 2, $1A for page 3, and $CD for page 4. A
pre-byte code applies only to the opcode which immediately follows it. That is, all instructions are
assumed to be single byte opcodes unless the first byte of the instruction happens to correspond
to one of the three pre-byte codes rather than a page 1 opcode.
MOTOROLA
CPU, ADDRESSING MODES AND INSTRUCTION SET
MC68HC11G5
12-4