MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 161

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
the original value of the D accumulator is automatically preserved in the index register while
the pointer is being manipulated in the D accumulator. When pointer calculations are finished,
another exchange simultaneously updates the index register and restores the D accumulator to its
former value.
The transfers between an index register and the stack pointer deserve additional comment. The
stack pointer always points at the next free location on the stack as opposed to the last thing that
was pushed onto the stack. The usual reason for transferring the stack pointer value into an index
register is to allow indexed addressing access to information that was formerly pushed onto the
stack. In such cases, the address pointed-to by the stack pointer is of no value since nothing has
been stored at that location yet. This explains why the value in the stack pointer is incremented
during transfers to an index register. There is a corresponding decrement of a 16-bit value as it is
transferred from an index register to the stack pointer.
12.3.3 Condition Code Register Instructions
This group of instructions allows the programmer to manipulate bits in the condition code register.
At first look, it may appear that there should be a set and a clear instruction for each of the 8 bits
in the condition code register while these instructions are present for only 3 of the 8 bits (C, I
and V). Upon closer consideration there are good reasons for not including the set and clear
instructions for the other five bits.
The stop disable (S) bit is an unusual case because this bit is intended to lock out the STOP
instruction for those who view it as an undesirable function in their application. Providing set and
clear instructions for this bit would make it easier to enable STOP when it was not wanted or disable
STOP when it was wanted. The TAP instruction provides a way to change S but cuts the chances
of an undesirable change to S in half because the value of the A accumulator at the time the TAP
instruction is executed determines whether or not S will actually change.
Clear Carry Bi
Clear Interrupt Mask Bit
Clear Overflow Bit
Set Carry Bit
Set Interrupt Mask Bit
Set Overflow Bit
Transfer A to CCR
Transfer CCR to A
Table 12-8. Condition Code Register Instructions
CPU, ADDRESSING MODES AND INSTRUCTION SET
Function
Mnemonic
SEC
SEV
CLC
CLV
TAP
TPA
CLI
SEI
INH
X
X
X
X
X
X
X
X
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