MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 22
MC68HC711G5
Manufacturer Part Number
MC68HC711G5
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC711G5.pdf
(195 pages)
- Current page: 22 of 195
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2.1.4.1 Factory Test Register (TEST1)
READ:
WRITE:
TILOP — Test Illegal Opcode
TPWSL — Pulse Width Modulation Scaled Clock
OCCR — Output Condition Code Register Status to Timer Port
CBYP1 — Timer Counter 1 Divider Chain By-pass
DISR — Disable Resets from COP and Clock Monitor
FCM — Force Clock Monitor Failure
MOTOROLA
2-4
RESET:
$103E
Any time (always zero if not in a test mode)
Only while SMOD = 1 (TEST or BOOT modes)
0 – Normal operation (trap on illegal opcodes)
1 – Stop giving LIR when an illegal opcode is found
This test mode allows testing of all illegal opcodes serially without servicing an
interrupt after each illegal opcode is received. LIR (inactive for illegal opcodes) is
used to monitor correct CPU operation.
0 – Normal operation
1 – Clock S (Scaled) from the PWM timer is output to and readable on the PWSCAL
0 – Normal operation
1 – The Condition Code bits H, N, Z, V, and C are driven out of the 5 most significant
0 – Normal operation
1 – 16-bit free running timer counter 1 is divided into 8-bit halves and the prescaler is
0 – Normal operation
1 – Regardless of other control bit states, COP and clock monitor will not generate a
When the device is reset in test or bootstrap mode (SMOD = 1), the DISR bit is initialized
to 1 so that resets from the COP and clock monitor are disabled. When reset in normal
modes, the DISR bit is initialized to 0.
0 – Normal operation
1 – Immediately generates a Clock Monitor failure reset. Note that the CME bit must
register. Normal writing of the PWSCAL register will still function.
bits (bits 3 – 7, respectively) of the timer I/O port to allow the test system to
monitor CPU operation.
by-passed. The system E-clock drives both halves directly.
system reset.
also be set for the reset to be forced.
TILOP TPWSL OCCR CBYP1 DISR
7
0
OPERATING MODES AND SIGNAL DESCRIPTION
6
0
5
0
4
0
3
0
FCM
2
0
FCOP
1
0
CBYP2
0
0
TEST1
MC68HC11G5
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