MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 58

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

control bit (IRV) in the OPT2 register is initialized to zero in normal modes to protect the system from
potential bus conflict with the external system. IRV is initialized to one if the MC68HC11G5 is reset
in a special mode (SMOD = 1) to enable internal read visibility for test and debug purposes. The IRQ
pin is configured for level sensitive operation (for wired-OR systems). The DLY control bit in the
OPTION register is set to specify that an oscillator start-up delay will be imposed upon recovery from
STOP mode. The clock monitor system is disabled by the CME bit in the OPTION register being set
to zero. When the system is reset in a special mode (SMOD = 1), the DISR control bit in the TEST1
register is initialized to logic one so that COP and clock monitor failures will not generate a reset.
In the normal modes (SMOD = 0), the DISR control bit is cleared to allow normal operation of the
COP and clock monitor systems.
5.2
INTERRUPTS
Excluding reset type interrupts, the MC68HC11G5 has 22 hardware interrupt sources and one
software interrupt source. These interrupts can be divided into two categories, maskable and non-
maskable. Twenty of the interrupt sources can be masked using the I bit in the condition code
register (CCR). All the on-chip hardware interrupts are individually masked by local control bits. The
software interrupt (SWI) is non-maskable. The external input to the XIRQ pin is considered a non-
maskable interrupt because it cannot be masked by software once it is enabled. However, it is
masked during reset and upon receipt of an interrupt signal at the XIRQ pin. Illegal opcode is also
a non-maskable interrupt.
5.2.1
Interrupt Vector Assignments
In all normal operating modes the interrupt vectors are located at the top of the address space
($FFC0 through $FFFF). In the bootstrap mode the interrupt vectors are located at $BFC0 through
$BFFF so that they exist in the internal bootstrap ROM. In the special test mode the interrupt vectors
also reside at $BFC0 – $BFFF but the internal bootstrap ROM is disabled so vectors are fetched
from external memory.
Table 5-2 provides a list of the interrupts with a vector location in memory for each, as well as the
condition code register and control bits that mask each interrupt. Figure 5-1 shows the interrupt
stacking order.
MOTOROLA
RESETS, INTERRUPTS AND LOW POWER MODES
MC68HC11G5
5-6