MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 82

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

6.4.11 Control Register 1 (TCTL1)
READ:
WRITE:
RESET:
OMx — Output Mode; OLx — Output Level
6.4.12 Timer Control Register 2 (TCTL2)
READ:
WRITE:
RESET:
EDGxB, EDGxA — Input Capture Edge Control
MOTOROLA
6-12
RESET:
RESET:
Any time.
Any time.
$00
These four pairs of control bits are encoded to specify the output action to be taken as
a result of a successful OCx compare (OC2 – OC5). When either OMx or OLx is set, the
pin associated with OCx becomes an output tied to OCx regardless of the state of the
associated DDR bit. Output compare OC5 only functions if the TO5I4 register is
programmed for output compare OC5 operation via the I4/O5 bit in the PACTL register.
Any time
Any time
$00
The level transition which triggers counter transfer is defined by the corresponding
input edge bits (EDGxB, EDGxA). These bit pairs are encoded to configure input
captures IC1 – IC4 to occur on rising edges, falling edges, either edge, or to inhibit
capture. Input capture 4 only functions if the TO5I4 register is programmed for input
capture IC4 operation by the I4/O5 bit in the PACTL register.
$1020
$1021
OMx
EDG4B
OM2
0
0
1
1
7
0
7
0
EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A
OL2
6
0
6
0
OLx
OM3
0
1
0
1
PROGRAMMABLE TIMER
5
0
5
0
OL3
4
0
4
0
OM4
3
0
3
0
Action taken upon successful compare
Timer disconnected from output pin logic
Toggle OCx output line
Clear OCx output line to zero
Set OCx output line to one
OL4
2
0
2
0
OM5
1
0
1
0
OL5
0
0
0
0
TCTL1
TCTL2
MC68HC11G5