MC68HC711G5 MOTOROLA [Motorola, Inc], MC68HC711G5 Datasheet - Page 87

• Manufacturer Part Number: MC68HC711G5
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC11G5
TO2I — Timer Overflow 2 Interrupt Enable
5/6I — Input Capture 5/Output Compare 6 Interrupt Enable
6/7I — Input Capture 6/Output Compare 7 Interrupt Enable
6.4.18 Miscellaneous Timer Interrupt Flag Register 2 (TFLG2)
The miscellaneous timer system flag register (TFLG2) contains flag bits which are set by hardware
when the corresponding timer interrupt condition occurs. Any flag bits in the TFLG1 register which
are set will remain set until they are cleared by writing ones to those bits.
READ:
WRITE:
RESET:
TO1F — Timer Overflow 1 Flag
RTIF — Real Time (Periodic) Interrupt Flag
PAOVF — Pulse Accumulator Overflow Flag
RESET:
0 – Interrupt inhibited
1 – Hardware interrupt requested when TO2F flag set
0 – Interrupt inhibited
1 – Hardware interrupt requested when 5/6F flag set
0 – Interrupt inhibited
1 – Hardware interrupt requested when 6/7F flag set
Any time.
Used in clearing mechanism (see above).
$00
Set when 16-bit free running timer 1 overflows from $FFFF to $0000. This bit is cleared
by writing to the TFLG2 register with bit 7 set.
Set when the tap point selected becomes set. This bit is cleared by writing to the
TFLG2 register with bit 6 set.
Set when the 8-bit pulse accumulator overflows from $FF to $00. This bit is cleared
by writing to the TFLG2 register with bit 5 set.
$1025
TO1F
7
0
RTIF
6
0
PAOVF
PROGRAMMABLE TIMER
5
0
PAIF
4
0
TO2F
3
0
5/6F
2
0
6/7F
1
0
0
0
0
TFLG2
MOTOROLA
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