FDC37C669_07 SMSC [SMSC Corporation], FDC37C669_07 Datasheet
FDC37C669_07
Related parts for FDC37C669_07
FDC37C669_07 Summary of contents
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PC 98/99 Compliant Super I/O Floppy Disk Controller with Infrared Support • 5 Volt Operation • Intelligent Auto Power Management • 16 Bit Address Qualification (Optional) • 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller ...
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FEATURES ............................................................................................................................................ 1 GENERAL DESCRIPTION..................................................................................................................... 3 PIN CONFIGURATION ........................................................................................................................... 4 DESCRIPTION OF PIN FUNCTIONS ..................................................................................................... 6 FUNCTIONAL DESCRIPTION ............................................................................................................. 17 SUPER I/O REGISTERS.................................................................................................................. 17 HOST PROCESSOR INTERFACE.................................................................................................. 17 FLOPPY DISK CONTROLLER........................................................................................................ 18 FLOPPY DISK CONTROLLER INTERNAL REGISTERS ................................................................ 18 COMMAND ...
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The SMSC FDC37C669 PC 95 Compatible Super I/O Floppy Disk Controller with Infrared Support utilizes SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C669 is PC95 compliant and is optimized for motherboard applications. The FDC37C669 supports both ...
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RXD2/IRRX TXD2/IRTX 89 nDSR2 90 nRTS2 91 nCTS2 92 93 nDTR2 DRV2/ADRX/IRQ_B 94 95 VSS nDACK_C 96 97 A10 98 NC DRQ_C 99 IOCHRDY 100 ...
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DRVDEN0 1 nMTR0 2 nDS1 3 nDS0 4 nMTR1 5 VSS 6 nDIR 7 nSTEP 8 nWDATA 9 FDC37C669 nWGATE 10 nHDSEL 11 nINDEX 12 nTRK0 100 PIN TQFP 13 nWRTPRT 14 VCC 15 nRDATA 16 nDSKCHG 17 DRVDEN1 18 ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL HOST PROCESSOR INTERFACE 48-51 Data Bus 0-7 D0-D7 53-56 44 nI/O Read nIOR 45 nI/O Write nIOW 46 Address Enable AEN 28-34 I/O Address A0-A10 41-43, 97 21,52, DMA Request ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 19, Interrupt IRQ_A Request 37-40, IRQ_C IRQ_D E, F, IRQ_E IRQ_F 27 Chip Select Input nCS 57 Reset RESET 16 nRead Disk Data nRDATA 10 nWrite nWGATE ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 7 Direction nDIR Control 8 nStep Pulse nSTEP 17 Disk Change nDSKCHG 4,3 nDrive Select nDS0,1 O,1 2,5 nMotor On 0,1 nMTR0,1 1 DRVDEN0 DRVDEN0 14 nWrite nWRTPRT Protected 13 ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 89 Transmit Data 2 TXD2/IRTX 78 Receive Data 1 RXD1 79 Transmit Data 1 TXD1 81,91 nRequest to nRTS1 Send nRTS2 (SYSOPT) (System Option) 83,93 nData Terminal nDTR1 Ready nDTR2 ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 82,92 nClear to Send nCTS1 nCTS2 80,90 nData Set Ready nDSR1 nDSR2 85,87 nData Carrier nDCD1 Detect nDCD2 BUFFER TYPE DESCRIPTION I Active low Clear to Send inputs for the ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 84,86 nRing Indicator nRI1 nRI2 PARALLEL PORT INTERFACE 73 nPrinter Select nSLCTIN Input 74 nInitiate Output nINIT 76 nAutofeed nAUTOFD Output BUFFER TYPE DESCRIPTION I Active low Ring Indicator inputs ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 77 nStrobe Output nSTROBE 61 Busy BUSY 62 nAcknowledge nACK 60 Paper End PE 59 Printer Selected SLCT Status 75 nError nERROR BUFFER TYPE DESCRIPTION OD24 An active low pulse ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 63-66 Port Data PD0-PD7 68-71 100 IOCHRDY IOCHRDY 24 nIDE Enable nIDEEN Interrupt IRQ_H Request H 25 nIDE Chip nHDCS0 Select 0 IRRX2 IRRX2 26 nIDE Chip nHDCS1 Select 1 ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 94 Drive 2 DRV2 Address X nADRX Interrupt IRQ_B Request B 23 IRQIN 58 PWRGD nGAMECS 98 I/O Power NC BUFFER TYPE DESCRIPTION I In PS/2 mode, this input indicates ...
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DESCRIPTION OF PIN FUNCTIONS QFP/ TQFP PIN NO. NAME SYMBOL 15,72 Power V CC 6,47, Ground GND 67,95 Note 1: Refer to Configuration Register 00 for information on the pull-ups for these pins! Note IDE does not decode for 377, ...
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V Vss (4) Vcc (2) MANAGEMENT nCS ADDRESS BUS nIOR nIOW AEN A0-A10 D0-D7 HOST DRQ_A-C CPU INTERFACE nDACK_A-C TC IRQA IRQ_C-F RESET IRQIN CLOCK IOCHRDY GEN nINDEX nTRK0 14.318 nDSKCHG CLOCK nWRPRT nWGATE FIGURE 1 - FDC37C669 BLOCK ...
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FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins, PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status ...
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PS/2 Model 30 Mode 7 INT DRQ PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicating direction a logic "1" outward. BIT 1 WRITE PROTECT Active high status of ...
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STATUS REGISTER B (SRB) Address F1 READ ONLY This register is read-only and monitors the state of several disk interface pins, in PS/2 and Model PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also 7 6 MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC37C669 does not require its characteristics modified for tape support. The contents of this register are not ...
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Table 7 - External Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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DRIVE RATE DATA RATE DRT1 DRT0 SEL1 SEL0 ...
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MAIN STATUS REGISTER Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status of the disk controller. The Main Status Register can be read at any RQM DIO NON DMA BIT ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment ...
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Table 15 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writeable WP pin became a "1" while the ...
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Table 16 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL NAME Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: The RESET pin of the FDC37C669, ...
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PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. ...
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A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then ...
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If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector hardware TC was received. The only difference between ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 18 - Description of Command Symbols SYMBOL NAME GAP Alters Gap 2 length when using Perpendicular Mode. GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). H/HDS Head Address ...
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Table 18 - Description of Command Symbols SYMBOL NAME N Sector Size Code This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. transferred is determined by the DTL ...
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Table 18 - Description of Command Symbols SYMBOL NAME SC Number of The number of sectors per track to be initialized by the Format Sectors Per Track command. The number of sectors per track to be verified during a Verify ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 19 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command SRT W RECALIBRATE DATA BUS ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result LOCK R 0 EIS EFIFO POLL R RELATIVE SEEK DATA BUS D5 ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS ...
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PHASE R Command PHASE R Command W Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was the Format command. EOT ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 23 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR TRANSFERRED TO HOST HEAD MT 0 Less than EOT Equal to EOT 0 1 Less than EOT Equal to EOT 0 Less than EOT Equal to EOT 1 1 Less than EOT Equal to EOT NC: No Change, ...
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Verify The Verify command is used to verify the data stored on a disk. This command acts exactly like a Read Data command except that no data is transferred to the host. Data is read from the disk and CRC ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 26 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 5.25" 4096 ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 3.5" FM 256 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command Terminate the Seek command 3) Read ID - Verify ...
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The values change with the data rate speed selection and are documented in Table 30. The Table 28 - Drive Control Delays (ms 500K 0 64 128 256 ...
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PRETRK - Pre-Compensation Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older ...
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Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that access a disk drive with perpendicular recording capability. command, the length of the Gap2 ...
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When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that drive to be set automatically to Perpendicular ...
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A status byte is returned immediately after issuing a LOCK command. This byte reflects the value of the LOCK bit set by the command byte. ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics ...
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PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. ...
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Table 30 - FDC Parallel Port Pins CONNECTOR PIN # CHIP PIN # ...
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The FDC37C669 incorporates two full function UARTs. They are compatible NS16450, the 16450 ACE registers and the NS16550A. The UARTs perform parallel conversion on received characters and parallel-to-serial conversion on characters. The data rates are independently programmable from 115.2K baud ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writing to this bit ...
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Table 32 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER PRIORITY LEVEL BIT 3 BIT 2 BIT 1 BIT Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit logic "0", the nDTR output is ...
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FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit 3 is set to a logic "1" whenever the stop ...
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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XMITTER are controlled separately, either one or both can be in the polled mode of operation. In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as ...
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Table 34 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 35 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 35 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 2 Data Bit 3 Enable Enable Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) Interrupt ID ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The FDC37C669's infrared interface provides a two-way wireless communications port using infrared as a transmission medium. infrared implementations have been provided in the FDC37C669, IrDA and Amplitude Shift Keyed IR. IrDA allows serial communication at baud rates up to 115K ...
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The FDC37C669 incorporates an IBM XT/AT compatible parallel port. The FDC37C669 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37C669 Configuration Registers ...
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Table 36 - Parallel Port Connector HOST PIN NUMBER CONNECTOR 1 77 2-9 71-68, 66- (1) = Compatible Mode (3) = High Speed Mode ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available in EPP mode. EPP 1.9 OPERATION When the ...
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Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. Chip may modify nWRITE and nPDATA in preparation for the next cycle. EPP 1.9 Read The ...
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Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can be used to extend the cycle time. The write cycle can complete when nWAIT is inactive high. Write Sequence of ...
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EPP SIGNAL EPP NAME TYPE nWRITE nWrite PD<0:7> Address/Data INTR Interrupt WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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Table 38 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. additional registers attach to an upper bit decode of the standard LPT port definition to Table 39 - ECP Register Definitions ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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Parallel Port to the CPU due to a low to high transition on the nACK input. Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no ...
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Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the ...
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Table 41 - Extended Control Register R/W 000: Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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PS/2 mode using program control of the control signals. Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = ...
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A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. DMA TRANSFERS Note: PDRQ - Currently selected Parallel Port DRQ ...
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The ECP requests programmed I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the FIFO using the appropriate direction and mode. Note: A threshold equivalent to a threshold of ...
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AUTO POWER MANAGEMENT Power management capabilities are provided for the following logical devices: floppy disk, UART 1, UART 2 and the parallel port. logical device, two types of power management are provided; direct powerdown and auto powerdown. Direct powerdown is ...
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Once awake, the FDC37C669 will reinitiate the auto powerdown timer for 10 ms. The part will powerdown again when all the powerdown conditions are satisfied. Register Behavior Table 43 reiterates the AT and PS/2 (including modes 30) configuration registers available. ...
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Table 43 - PC/AT and PS/2 Available Registers Base + Address Access to these registers DOES NOT wake up the part 00H 01H 02H 03H 04H 06H 07H 07H Access to these registers wakes up the part 04H 05H Note ...
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FDD Interface Pins All pins in the FDD interface which can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Table 45 - State of Floppy Disk Drive Interface Pins in Powerdown FDD Pins RDATA ...
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UART Power Management Direct power management is controlled by CR2 bits 3 and 7. Refer to CR2 bits 3 and 7 for more information. Auto Power Management is enabled by CR7 bits 5 and 6. When set, these bit allows ...
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INTEGRATED DRIVE ELECTRONICS INTERFACE The IDE interface enables hard disks with embedded controllers (AT and XT interfaced to the host processor. The following definitions are for reference only. registers are not implemented FDC37C669. Access to these registers is ...
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COMMAND RESTORE (RECALIBRATE) SEEK READ SECTOR WRITE SECTOR FORMAT TRACK READ VERIFY DIAGNOSE SET PARAMETERS Bit definitions: r: specifies the step rate to be used for the command set, 16 bit DMA used for the ...
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AT HOST ADDRESSABLE REGISTERS ADDR R/W D15 D14 D13 D12 D11 D10 000H DATA REGISTER (REDIRECTED TO FIFO) ADDR R 001H R BB CRC - 001H W CYLINDER NUMBER +4 002H R/W NUMBER OF SECTORS 003H R/W ...
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MISCELLANEOUS AT REGISTERS ADDR R 3F6H/3 R BSY RDY WF 76H 3F6H/3 W RESERVED 76H 3F7H nWG nHS3 77H 3F7H 77H DRQ CD INDEX HS3EN ADPTR ...
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The configuration of the chip is programmable through software selectable registers. CONFIGURATION REGISTER ADDRESS The address at which the Registers are located is controlled by the nRTS2 pin. The state of the nRTS2 pin is latched by the trailing edge ...
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ENTER CONFIGURATION MODE ;-----------------------------' MOV DX,3F0H MOV AX,055H ; CLI ; disable interrupts OUT DX,AL OUT DX,AL STI ; enable interrupts ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx ;-----------------------------' MOV DX,3F0H MOV AL,00H OUT DX,AL ; Point to CR0 MOV ...
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Table 46 - Configuration Registers Default DB7 DB6 28H CR00 Valid 9CH CR01 Lock CRx 88H CR02 UART2 PWR 78H CR03 ADRX/ IDENT DRV2/ IRQ_B 00H CR04 ALT I/O EPP Type 00H CR05 Reserved EXTx4 FFH CR06 Floppy Drive D ...
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Configuration Register Description The configuration registers consist of the Configuration Select Register Configuration Registers CR-00 -CR-29. configuration select register is written to by writing to port 3F0H (or 370H). Configuration Registers CR-00; CR-29 are accessed by reading or writing to ...
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CR01 This register can only be accessed in the Configuration Mode and after the CSR has BIT NO. BIT NAME 0,1 Reserved 2 Parallel Port Power (see note _PWRDN) 3 Parallel Port Mode 4 Reserved 5,6 Reserved 7 Lock CRx ...
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CR03 This register can only be accessed in the Configuration Mode and the CSR has been BIT NO. BIT NAME 0 PWRGD/ GAMECS 1 Enhanced Floppy Mode 2 3 Reserved 4 DRVDEN1 5 MFM 6 IDENT 7,2 ADRx/ DRV2 EN/ ...
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CR04 This register can only be accessed Configuration Mode and the CSR has been Table 51 - CR04 - Parallel and Serial Extended Setup Register BIT NO. BIT NAME 1,0 Parallel Port Extended Modes 2,3 Parallel Port FDC 4 MIDI ...
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CR05 This register can only be accessed in the Configuration Mode and the CSR has been Table 52 - CR05- Floppy Disk and IDE Extended Setup Register BIT NO. BIT NAME 0,1 Reserved 2 FDC DMA Mode 4,3 DenSel 5 ...
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CR07 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 07H. The default value of BIT NO. BIT NAME 0,1 Floppy Boot 2 Reserved 3 Reserved 4 Parallel Port Enable 5 ...
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CR08 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 08H. The default value of this register after power up is 00H. This is the lower 4 bits (ADRA7:4) for the ...
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CR0C This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 0CH. The default value of this BIT NO. BIT NAME 0 UART 2 RCV Polarity 1 UART 2 XMIT Polarity 2 ...
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CR0F This register can only be accessed the Configuration Mode and BIT NO CSR has been initialized to 0FH. The default after the value of this register after power up is ...
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CR10 This register can only be accessed in the Configuration Mode and after the CSR has been BIT NO. BIT NAME Reserved Reserved - READ ONLY. A read returns Pll Gain This bit controls ...
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CR12-CR1D These registers are reserved. The default value of these registers after power up is 00H. CR1E This register can only be accessed in the Configuration Mode and after the CSR has been DB7 DB6 DB5 ADR9 ADR8 ADR7 DB1 ...
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CR1F This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 1FH. The default value FDD3 DT0 DT1 DT0 DTx = Drive Type select DRVDEN0 DT0 DT1 (Note) 0 ...
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CR21 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 21H. The default value of this register after power up is 3CH. register is used to select the base address of ...
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CR24 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 25H. The default value of this register after power up is 00H. This register is used to select the base address ...
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CR27 This register can only be accessed in the Configuration Mode and after the CSR has been initialized to 27H. The default value of this register after power up is 00H. This register is used to select the IRQ for ...
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Table 60 - UART Interrupt Operation Table UART1 UART1 UART1 IRQ OUT2 bit Output State OUT2 bit asserted 1 de-asserted asserted 1 asserted 1 de-asserted 1 de-asserted asserted 1 ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range ......................................................................................... 0 Storage Temperature Range .......................................................................................... -55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ............................................................... V Negative Voltage on any pin, with ...
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PARAMETER SYMBOL Input Leakage (All I and IS buffers except PWRGD) Low Input Leakage I IL High Input Leakage Input Current OH PWRGD I/O 24 Type Buffer Low Output Level V OL High Output Level V OH ...
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PARAMETER SYMBOL OD 24 Type Buffer Low Output Level V OL Output Leakage Type Buffer Low Output Level V OL High Output Level V OH Output Leakage Type Buffer V OL ...
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TIMING DIAGRAMS A X, AEN, nIOCS16 nIOR t 4 DATA (D0-D7) P D0-PD7, nERR SLCT, nACK, BUSY FINTR nIOR/nIOW PINTR NOTE: P INTR is the interrupt assigned to the Parallel Port FINTR is the ...
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EN S16 t1 nIOW DAT A (D0-D7) FINTR PI NTR NOTE: PINTR is the interrupt assigned to the Paral lel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 A0-A9, AEN , ...
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AEN FD RQ, P DRQ t1 FDA CKX PDA CKX t14 t6 nIOR t5 or nIOW DATA (DO-D7) TC NOTE: FDRQ refers to the DRQ assigned to the Floppy Disk PDRQ refers to the DRQ assigned to the Parall el ...
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X1K nRE SET Name Des cription Clo ck Cycl eTime for 14.318MHZ t1 Clock Hig h Time/Low Time for t2 1 4.318MHZ Clo ck Cycl e Time for 32KHZ t1 t2 Clo ck High Time/Low Time for 3 2KHz Clock ...
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nSTEP nDS0-3 nI NDEX nRDATA nWDAT A nIOW t 9 nDS0-1, nM TR0-1 (AT Mode timin g only) Parameter t1 nDIR Set Up to nSTEP Low t2 nSTEP Active Time Low t3 nDIR Hol d Time ...
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IRQx nCTSx, nD SRx, nDCDx t2 IRQx nIOW IRQx nIOR nR Ix Parameter t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Del ay from nC TSx, n DSRx, nDC Inactive De lay ...
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AEN, nIOCS nIDEEN, nHDCS x Par ameter t1 n IDEENL O, nIDEEN HI, nH DCSx Delay from AEN, nIOC S1 6 nIDEENLO, nIDEENH I, nHDCSx Delay t2 from AX n IDEEN LO De lay from nIDEENH ...
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DATA IRRX n IRRX Parameter t1 Pul se Wid 115 kbau d t1 Pulse Width kbau d t1 Pulse Width kbau d t1 ...
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DATA IRTX nIRTX Parameter t1 Pu lse Width at 1 15kba ud t1 Pulse Width at 57.6kba ud t1 Pulse Width at 38.4kba ud t1 Pulse Width at 19.2kba ud t1 Pulse ...
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DATA IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Mod ulated Output Bit Time t2 Off Bit Time t3 Modul ated Output " On" t4 Modul ated Outp ut "Off" t5 Modul ...
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DATA MIR nMIR RX Parameter t1 Mo dula ted Ou tpu t Bit Time t2 Off Bit Time t3 Modu lated Output "On" t4 Modu ...
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PD0 nINIT, nSTROBE. nAUTOFD, SLCTIN PIN TR (SP P) nACK t2 PI NTR (ECP or EPP E nabled) nF AULT (ECP) nERROR (E CP) PI NTR Par ameter t1 nINIT, n STROBE, nAUTOFD Dela ...
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AX SD<7:0> nIOW RDY nWR ITE t1 PD<7: 0> nDATAST nADDRSTB nWAIT Parameter t1 nIOW Ass erted t o PDA T A Valid t2 ...
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AX t19 IOR SD<7:0> t8 IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> t28 t1 t14 DATASTB ADDRSTB nWAIT Timin g paramete r tabl the EPP Data or Addre ss Read Cycl e is found on next pag ...
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Parameter t1 PDATA Hi-Z to Comman d Asserted t2 nIOR Asserted to PD ATA nWAIT Deasser ted to Comma nd Dea sserted t4 Comma nd Dea sserted to PDATA Hi ommand Asser ted to PDATA ...
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A X SD<7:0> t17 t 8 nIOW t10 t20 IOCHRD Y t13 nWRITE t 1 PD<7:0> t16 t 3 nDATAST nAD DRSTB nWAIT Param eter t1 nIOW Ass erted t o PDA alid t2 Command D esssert ...
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AX t19 nIOR S D<7:0> IOCHRDY nWRITE t5 P D<7:0> t23 nDATAS TB nADD RS TB nWAIT Parameter t 2 nIOR Deas sert ed to Command Deass erted t 3 nWAIT Asserted to IOC HRDY D eass erted ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next ...
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Compatible Mode (the control signals, by tradition, are as open-collector), the drivers are dynamically changed from open-collector to totem-pole. The timing for the dynamic driver change is specified PDATA nS T ROBE BUSY Parameter t1 DATA Vali ...
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PDA TA<7:0> TROBE t6 BUSY Parameter t1 n AUTOFD Va lid to nSTROBE Asserted t2 PDATA Va lid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Cha nged Deasser ted to ...
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PDATA<7: 0> nACK t 4 nAUTOFD Parameter t1 PDATA Va lid to nACK Asserted t2 nAUTOFD Deasserte d to PDATA C hang ed t3 nACK Asse rte AUTOFD Deasserted t4 nACK D easser ...
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-C- MIN MAX MIN 0 24 ...
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-C- DIM Notes: Coplanarity is 0.100mm maximum. 1 Tolerance on the position of the ...
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FDC37C669 ERRATA SHEET PAGE SECTION/FIGURE/ENTRY 1 Features 4 PIN CONFIGURATION/Pin No Description of Pin Functions 14 Buffer Type Descriptions 15 Block Diagram 119 Table 46/Last Row 136 MAXIMUN GUARANTEED RATINGS 136 DC ELECTRICAL CHARACTERISTICS 136 - ...
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ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...