FDC37N769_07 SMSC [SMSC Corporation], FDC37N769_07 Datasheet
FDC37N769_07
Related parts for FDC37N769_07
FDC37N769_07 Summary of contents
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Super I/O Controller with Infrared Support for Portable Applications 3.3 Volt Operation Intelligent Auto Power Management 16 Bit Address Qualification (Optional) 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible ...
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The SMSC FDC37N769 is a 3.3v PC 97-compliant Super I/O Controller with Infrared support. The FDC37N769 utilizes SMSC’s proven SuperCell technology and is optimized for motherboard applications. incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16-byte ...
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GENERAL DESCRIPTION................................................................................................................. 2 PIN CONFIGURATION ...................................................................................................................... 7 PIN DESCRIPTION ............................................................................................................................. 8 BUFFER TYPE PER PIN........................................................................................................................ ..................................................................................................................... 14 UFFER YPE UMMMARY O D ................................................................................................................................... 14 UTPUT RIVERS FUNCTIONAL DESCRIPTION........................................................................................................ ................................................................................................................ 16 OST ROCESSOR ...
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Relative Seek...................................................................................................................................... 54 Perpendicular Mode.......................................................................................................................... 55 LOCK................................................................................................................................................. 56 ENHANCED DUMPREG.................................................................................................................. ARALLEL ORT LOPPY ISK ONTROLLER SERIAL PORT (UART) ..................................................................................................................... ......................................................................................................................... 58 EGISTER ESCRIPTION RECEIVE BUFFER REGISTER (RB) ............................................................................................... 59 TRANSMIT BUFFER ...
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AUTO POWER MANAGEMENT .................................................................................................... 91 FDC P M ................................................................................................................... 91 OWER ANAGEMENT DSR From Powerdown...................................................................................................................... 91 Wake Up From Auto Powerdown...................................................................................................... 92 Register Behavior .............................................................................................................................. 92 Pin Behavior...................................................................................................................................... 92 UART P M ............................................................................................................... 94 OWER ANAGEMENT P P ..................................................................................................................................... 94 ...
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CR2D ............................................................................................................................................... 112 CR2E ............................................................................................................................................... 112 CR2F ............................................................................................................................................... 112 OPERATIONAL DESCRIPTION................................................................................................... 113 MAXIMUM GUARANTEED RATINGS .......................................................................................... 113 DC ELECTRICAL CHARACTERISTICS ......................................................................................... 113 AC TIMING....................................................................................................................................... 116 H T ....................................................................................................................................... 116 OST IMING FDD T ........................................................................................................................................ 120 IMING ........................................................................................................................... ...
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RXD1 76 TXD1 77 nDSR1 78 nRTS1 79 nCTS1 80 nDTR1 81 nRI1 82 nDCD1 83 nRI2 84 nDCD2 85 RXD2/IRRX 86 TXD2/IRTX 87 nDSR2 88 nRTS2 89 nCTS2 90 nDTR2 91 DRV2/ADRX/IRQ_B 92 VSS 93 nDACK_C 94 A10 95 ...
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Table 1 - DESCRIPTION OF PIN FUNCTIONS TQFP PIN # NAME SYMBOL 46-49 Data Bus 0- D0-D7 51- nI/O Read nIOR 43 nI/O Write nIOW 44 Address AEN Enable 26-32 Address A0-A10 39-41, Bus 95 19,50, DMA DRQ_A ...
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TQFP PIN # NAME SYMBOL 7 nWrite nWDATA Data 9 nHead nHDSEL Select 5 Direction nDIR Control 6 nStep nSTEP Pulse 15 Disk nDSKCHG Change 2, 1 nDrive nDS0,1 Select 0,1 100, 3 nMotor On nMTR0, 1 0,1 99 Drive ...
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TQFP PIN # NAME SYMBOL 81,91 nData nDTR1 Terminal Ready nDTR2 80,90 nClear to nCTS1 Send nCTS2 78,88 nData Set nDSR1 Ready nDSR2 83,85 nData nDCD1 Carrier Detect nDCD2 82,84 nRing nRI1 Indicator nRI2 TQFP PIN # NAME SYMBOL 71 ...
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TQFP PIN # NAME SYMBOL 72 nInitiate nINIT Output/ FDC nDirection Control 3 (Note ) nDIR 74 nAutofeed nAUTOFD Output/ FDC nDensity Select 3 (Note ) nDENSEL 75 nStrobe nSTROBE Output/ FDC nDrive Select 0 3 (Note ) nDS0 59 ...
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TQFP PIN # NAME SYMBOL 66 Port Data PD3 3/FDC nRead Disk nRDATA Data 64 Port Data PD4 4/FDC nDisk nDSKCHG Change 63 Port Data 5 PD5 62 Port Data PD6 6/FDC nMotor On nMTR0 0 61 Port Data 7 ...
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TQFP PIN # NAME SYMBOL 18 14.318 CLK14 MHz Input Clock 23 IR Receive IRRX2 Transmit IRTX2 2 5 (Note ) 92 Drive 2/ DRV2 Address X/ Interrupt Request B nADRX IRQ_B 21 IR Mode/ IR IRMODE ...
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Buffer Type Summmary Table 2 below describes the buffer types shown in Table 1. All values are specified at V Table 2 - FDC37N769 3.3V Buffer Type Summary BUFFER TYPE IO12 Input/Output. 12mA sink; 6mA source O12 Output. 12mA sink; ...
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Vss (4) Vcc (2) nCS nIOR nIOW AEN A0-A10 D0-D7 HOST CPU DRQ_A-C INTERFACE nDACK_A-C TC IRQA IRQ_C-F IRQ_H RESET IRQIN CLOCK IOCHRDY GEN 14.318 CLOCK SMSC DS – FDC37N769 PWRGD/nGAMECS POWER MANAGEMENT DATA BUS ADDRESS BUS CONFIGURATION REGISTERS CONTROL ...
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Super I/O Registers Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base addresses must be set in the configuration registers before accessing these devices. The base addresses of the ...
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PS/2 Interface Mode When IDENT is low and MFM is high PS/2 Interface mode is selected. This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the Digital Output Register becomes a “don’t care,” FINTR ...
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Bit 4 Active low status of the TRK0 disk interface input. Step, Bit 5 Active high status of the STEP output disk interface output pin. nDRV2, Bit 6 Active low status of the DRV2 disk interface input pin, ...
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Motor Enable 0, Bit 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Motor Enable 1, Bit 1 Active high status of the MTR1 ...
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SELECT 0, Bit 5 Active low status of the DS0 disk interface output. nDRIVE SELECT 1, Bit 6 Active low status of the DS1 disk interface output. nDRV2, Bit 7 Active low status of the DRV2 disk interface input. ...
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MOTOR ENABLE 3, Bit 7 The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic “1” in this bit causes the output to go active. Drive Select Encoding The FDC37N769 can support two types of drive select ...
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Table 14 - External 2-to-4 Drive Decode: Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit ...
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Drive Type ID, Bits The Drive Type ID bits depend on the last drive selected in the Digital Output Register and the Drive Type IDs that are programmed in configuration register 6 (Table 18). DIGITAL OUTPUT REGISTER ...
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DATA RATE SELECT REGISTER (DSR) The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write precompensation, power down status, and software reset (Table 20). Note: the data rate is programmed ...
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PRECOMP SELECT DRIVE RATE DATA RATE SELECT SELECT (CR0B) (DSR) DRT1 DRT0 SEL1 ...
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Table 23 - Drive Rate Table (Recommended) DRIVE RATE DRT1 DRT0 DATA REGISTER (FIFO) The Data Register (Base Address + 5) is used to transfer all command parameter information, disk data and result status ...
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FIFO THRESHOLD 2Mbps EXAMPLES 1 byte 1 x 4μs - 1.5μs = 2.5μs 2 bytes 2 x 4μs - 1.5μs = 6.5μs 8 bytes 8 x 4μs - 1.5μs = 30.5μs 15 bytes 15 x 4μs - 1.5μs = 58.5μs ...
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Model 30 Interface Mode 7 DSK CHG RESET N/A CONDITION Data Rate Select, Bits These bits control the data rate of the floppy controller. See Table 22 for the settings corresponding to the individual data rates. The ...
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Data Rate Select, Bits These bits determine the data rate of the floppy controller. See Table 22 for the appropriate values. No Precompensation, Bit 2 This bit can be set by software, but it has no functionality. ...
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BIT NO. SYMBOL NAME 0 MA Missing Address Mark BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address ...
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BIT NO. SYMBOL NAME Write Protected Track Head Address 1,0 DS1,0 Drive Select Reset There are three sources of system reset on the FDC: the RESET pin of the FDC37N769, ...
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After the last parameter byte is received, RQM remains “0” and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command ...
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Data Transfer Termination The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and end-of- track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a ...
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Table 35 - Description of Command Symbols SYMBOL NAME C Cylinder Address D Data Pattern D0, D1, D2, Drive Select 0-3 D3 DIR Direction Control DS0, DS1 Disk Drive Select DTL Special Sector Size EC Enable Count EFIFO Enable FIFO ...
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SYMBOL NAME N Sector Size Code NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector Address RCN Relative Cylinder Number SC Number of Sectors Per ...
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Instruction Set PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – FDC37N769 Table 36 - Instruction Set READ DATA DATA BUS ...
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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W MT MFM ...
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PHASE R/W D7 Command W MT MFM Execution Result SMSC DS – FDC37N769 WRITE DELETED DATA DATA BUS ...
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PHASE R/W D7 Command Execution Result SMSC DS – FDC37N769 READ A TRACK DATA BUS MFM ...
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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W 0 Result R 1 SMSC DS – FDC37N769 VERIFY DATA ...
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PHASE R/W D7 Command Execution for W Each Sector Repeat Result PHASE R/W D7 Command Execution SMSC DS ...
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PHASE R/W D7 Command W 0 Result R R DATA BUS D7 PHASE R Command W ─── SRT ─── W ────── HLT ────── PHASE R/W D7 Command Result R PHASE R/W D7 Command W ...
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PHASE R/W D7 Command Execution W PHASE R/W D7 Command PHASE R/W D7 Command W 0 Execution Result LOCK R 0 ...
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PHASE R/W D7 Command PHASE R/W D7 Command W Result R SMSC DS – FDC37N769 ──────── ST1 ──────── ──────── ST2 ──────── ──────── C ──────── ──────── H ──────── ──────── R ──────── ──────── ...
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PHASE R/W Command W LOCK Result returned if the last command that was issued was the Format command. EOT is returned if the last command was a Read or Write. Note: These bits are used internally only. ...
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The amount of data which can be handled with a single command to the FDC depends upon MT (multi-track) and N (number of bytes/sector). The Multi-Track function (MT) allows the FDC to read data from both sides of the diskette. ...
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Table 39 - Skip Bit vs. Read Data Command SK BIT VALUE DATA ADDRESS MARK TYPE ENCOUNTERED 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data Read Deleted Data This command is the same as the Read ...
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Read A Track This command is similar to the Read Data command except that the entire data field is read continuously from each of the sectors of a track. Immediately after encountering a pulse on the nINDEX pin, the FDC ...
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Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning of the Data Field instead of the normal Data Address Mark. This command is ...
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FDC encounters a pulse on the IDX pin again and it terminates the command. Table 44 contains typical values for gap fields which are dependent upon the size of the sector and ...
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FORMAT FM 5.25” Drives MFM FM 3.5” Drives MFM GPL1 = suggested GPL values in Read and Write commands to avoid splice point between data field and ID field of contiguous sections. GPL2 = suggested GPL value in Format A ...
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Recalibrate This command causes the read/write head within the FDC to retract to the track 0 position. The FDC clears the contents of the PCN counter and checks the status of the nTR0 pin from the FDD. As long as ...
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The Seek, Relative Seek, and Recalibrate commands have no result phase. The Sense Interrupt Status command must be issued immediately after these commands to terminate them and to provide verification of the head position (PCN). The ...
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E 56 112 F 60 120 0 63.5 The choice of DMA or non-DMA operations is made by ...
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RCN - Relative Cylinder Number that determines how many tracks to step the head in or out from the current track number. The Relative Seek command differs from the Seek command in that it steps the head the absolute number ...
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For the Write Data case, the FDC activates Write Gate at the beginning of the sync field under the conventional mode. The controller then writes a new sync field, data address mark, data field, and CRC as shown in Figure ...
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COMPATIBILITY The FDC37N769 was designed with software compatibility in mind fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, ...
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CONNECTOR PIN # CHIP PIN # Note : These pins are outputs in mode PPFD2. Inputs in mode PPFD1 For ACPI compliance the FDD pins that are multiplexed onto the Parallel Port must function independently ...
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DLAB NOTE : DLAB is Bit 7 of the Line Control Register RECEIVE BUFFER REGISTER (RB) The Receive Buffer register (Address Offset = 0H, DLAB = 0, READ ONLY) holds the received incoming ...
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Interrupt Pending, Bit 0 The Interrupt Pending bit can be used in either a hardwired prioritized or polled environment to indicate whether an interrupt is pending. When bit logic “0”, an interrupt is pending and the contents ...
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FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT BIT BIT BIT FIFO CONTROL REGISTER (FCR) The FIFO Control register (Address Offset = 2H, DLAB = X, WRITE) appears at the same location as the IIR. ...
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Word Length Select, Bits The Word Length Select bits specify the number of bits in each transmitted or received serial character. Note: the Start, Stop and Parity bits are not included in the word length. The encoding ...
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Stop Bits, Bit 2 The Stop Bits bit specifies the number of stop bits in each transmitted or received serial character. Table 55 describes the Stop Bits encoding. Note: The receiver ignores stop bits beyond the first, regardless of the ...
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OUT1, Bit 2 The OUT1 bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. OUT2, Bit 3 The OUT2 bit is used to enable ...
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FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. The Serial Port will try to resynchronize after a framing error this, it assumes that the ...
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Clear To Send, Bit 4 The Clear To Send bit is the complement of the Clear To Send input (nCTS). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to nRTS in the ...
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DIVISOR USED TO DESIRED GENERATE 16X BAUD RATE CLOCK 9600 19200 38400 57600 115200 230400 460800 SMSC DS – FDC37N769 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 12 0.16 6 0.16 3 0.16 2 1.6 1 0.16 32770 0.16 32769 ...
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The Affects of RESET on the UART Registers The RESET Function (Table 57) details the affects of RESET on each of the Serial Port registers. REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. ...
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The transmitter holding register interrupt (02H) occurs when the XMIT FIFO is empty cleared as soon as the transmitter holding register is written characters may be written to the XMIT FIFO while servicing ...
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Note 2: When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty. Table 59 - Individual UART Channel Register Summary Continued BIT 2 BIT 3 Data Bit 2 Data Bit ...
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Notes On Serial Port FIFO Mode Operation GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD as ...
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The IrDA V1.1 (FIR) and Consumer IR formats are driven by the SCE registers. Descriptions of these registers can be found in the SMSC Infrared Communications Controller Specification. The Base Address for the SCE registers is programmed in CR2B, the ...
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If the start bit of another character is received during this time-out, the timer is restarted after the new character is received. increments (see section CR2D on page 112). IrCC Block RAW COM TV ASK OUT ...
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PARALLEL PORT The FDC37N769 incorporates an IBM XT/AT compatible parallel port. The FDC37N769 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37N769 ...
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HOST SMSC PIN NUMBER CONNECTOR 1 2-9 69-66, 64- (1) = Compatible Mode (3) = High Speed Mode Note: For the cable interconnection required for ECP support and the Slave Connector pin ...
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BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic “0” means an error has been detected; a logic “1” means no error has ...
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BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ ...
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During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always write mode and the nWRITE signal to always be asserted. Software Constraints Before an EPP cycle is ...
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EPP 1.7 OPERATION When the EPP 1.7 mode is selected in the configuration register, the standard and bi-directional modes are also available EPP Read, Write or Address cycle is currently executing, then the PDx bus is in the ...
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EPP SIGNAL EPP NAME WAIT nWait DATASTB nData Strobe RESET nReset ADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status NERR Error PDIR Parallel Port Direction Note 1: SPP and EPP can use 1 common register. Note 2: nWrite ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. High performance half-duplex forward and reverse channel Interlocked handshake, for ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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NAME TYPE NInit O NSelectIn O Register Definitions The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The additional registers attach to an upper bit decode of the standard ...
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Mode 011 (ECP FIFO - Address/RLE) A data byte written to this address is placed in the FIFO and tagged as an ECP Address/RLE. The hardware at the ECP port transmits this byte to the peripheral automatically. The operation of ...
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BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid and a logic 0 means that the printer ...
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Register A) ADDRESS OFFSET = 400H Mode = 111 This register is a read only register. When read, 10H is returned. This indicates to the system that this is an 8-bit implementation. (PWord = 1 byte) cnfgB (Configuration ...
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BIT 1 full Read only 1: The FIFO cannot accept another byte or the FIFO is completely full. 0: The FIFO has at least 1 free byte. BIT 0 empty Read only 1: The FIFO is completely empty. 0: The ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Table 70 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data The FDC37N769 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is ...
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The following paragraphs detail the operation of the FIFO flow control. In these descriptions, <threshold> ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value ...
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Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO this time the FIFO is full bytes may be ...
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Wake Up From Auto Powerdown If the FDC enters the powerdown state through the auto powerdown mode, wake up will occur after a reset or by access to the specific registers shown below hardware or software reset is ...
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System Interface Pins Table 72 gives the state of the system interface pins in the powerdown state. Pins unaffected by the powerdown are labeled “Unchanged”. Input pins are “Disabled” to prevent them from causing currents internal to the FDC37N769 when ...
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FDD Interface Pins All pins in the FDD interface that can be connected directly to the floppy disk drive itself are either DISABLED or TRISTATED. Pins used for local logic control or part programming are unaffected. Table 73 depicts the ...
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The EPP logic is in powerdown under any of the following conditions: 1. EPP is not enabled in the configuration registers. 2. EPP is not selected through ecr while in ECP mode. The ECP logic is in powerdown under any ...
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Exiting the Configuration State To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The FDC37N769 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until ...
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Configuration Select Register (CSR) The Configuration Select Register can only be accessed when the FDC37N769 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register ...
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DEFAULT INDEX DB7 00H CR2C 03H CR2D 00H CR2E 00H CR2F CR00 CR00 can only be accessed in the configuration state and after the CSR has been initialized to 00H. The default value of this register after power up is ...
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CR02 CR02 can only be accessed in the configuration state and after the CSR has been initialized to 02H. The default value of this register after power up is 88H (Table 78). BIT NO. BIT NAME 0:2 Reserved 3 UART1 ...
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CR04 CR04 can only be accessed in the configuration state and after the CSR has been initialized to 04H. The default value after power up is 00H (Table 80). Table 80 - CR04: Parallel and Serial Extended Setup Register BIT ...
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CR05 CR05 can only be accessed in the configuration state and after the CSR has been initialized to 05H. The default value after power up is 00H (Table 81). Table 81 - CR05: Floppy Disk Setup Register BIT BIT NO. ...
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FDC OUTPUT DRVDEN1 CONTROL CONTROL (CR05.1) (CR03. CR06 CR06 can only be accessed in the configuration state and after the CSR has been initialized to 06H. The default value of this register after power up is FFH ...
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CR08 CR08 can only be accessed in the configuration state and after the CSR has been initialized to 08H. The default value of this register after power up is 00H (Table 85). CR08 contains the lower 4 bits (ADRA7:4) for ...
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CR0B CR0B can only be accessed in the configuration state and after the CSR has been initialized to 0BH. The default value of this register after power up is 00H (Table 90). CR0B indicates the Drive Rate table used for ...
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CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the FDC37N769 Device ID. The default value of this register after power up is ...
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CR11 CR11 can only be accessed in the configuration state and after the CSR has been initialized to 11H. The default value of this register after power up is 80H (Table 94). CR11 is a test control register and all ...
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CR16 CR161 can only be accessed in the configuration state and after the CSR has been initialized to 16H. CR16 shadows the bits in the write-only UART2 run-time FCR register (Table 97). Table 97 - CR16: UART2 FCR Shadow Register ...
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Upper Address Decode requirements: nCS=’0’ and A10=’0’ are required to qualify the GAMECS output. CR03.0, the PWRGD/GAMECS control bit, overrides the selection made by the GAMECS Configuration Bits. CR1F CR1F can only be accessed in the configuration state and after ...
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CR21 - CR22 Registers CR21 - CR22 are Reserved. Reserved bits cannot be written and return 0 when read. CR23 CR23 can only be accessed in the configuration state and after the CSR has been initialized to 23H. The default ...
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CR26 CR26 can only be accessed in the configuration state and after the CSR has been initialized to 26H. value of this register after power up is 00H (Table 108). CR26 is used to select the DMA for the FDC ...
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UART1 UART1 UART1 IRQ OUT2 bit Output State 1 asserted 1 asserted 1 de-asserted 1 de-asserted It is the responsibility of the software to ensure that two IRQ’s are not set to the same IRQ number. Potential damage to chip ...
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CR2C CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH. The default value of this register after power up is 00H (Table 113). Bits D[3:0] of this register are used to ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS Operating Temperature Range........................................................................................................................... 0 Storage Temperature Range ............................................................................................................................-55 Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325 Positive Voltage on any pin, with respect to Ground ......................................................................................................+5.5V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V ...
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O12 Type Buffer Low Output Level High Output Level Output Leakage PARAMETER O12PD Type Buffer Low Output Level High Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level Output Leakage OD14 Type Buffer Low Output Level ...
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PARAMETER O4 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby ChiProtect (SLCT, PE, BUSY, nACK, nERROR) Backdrive Protect (nSLCTIN, nINIT, nAUTOFD, nSTROBE, PD[7:0]) Note ...
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SIGNAL NAME DRVDEN[1:0] TXD nRTS nDTR PD[7:0] nSLCTIN nINIT nALF nSTB Host Timing AX, AEN, nIOCS16 nIOR DATA (D0-D7) PD0-PD7, nERR, PE, SLCT, nACK, BUSY FINTR nIOR/nIOW PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the ...
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AX, AEN, nIOCS16 t1 nIOW DATA (D0-D7) FINTR PINTR PINTR is the interrupt assigned to the Parallel Port FINTR is the interrupt assigned to the Floppy Disk Parameter t1 A0-A9, AEN, nIOCS16 Set Up to nIOW Low t2 nIOW Width ...
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FDRQ , P DRQ FDACK X P DACK X nIO R or nIOW DATA (DO -D7) TC FDRQ refers to the DRQ assigned to the Floppy Disk P DRQ refers to the DRQ assigned to the Parallel ...
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X1K nRESET Parameter Clock CycleTime for 14.318MHZ t1 Clock High Time/Low Time for t2 14.318MHZ Clock Cycle Time for 32KHZ t1 Clock High Time/Low Time for 32KHz t2 Clock Rise Time/Fall Time (not shown) t4 nRESET Low Time The nRESET ...
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FDD Timing nDIR nSTEP nDS0-3 nINDEX nRDATA nW DATA nIOW nDS0-1, nM TR0-1 (AT Mode timing only) t1 nDIR Set Up to nSTEP Low t2 nSTEP Active Time Low t3 nDIR Hold Tim e After nSTEP t4 nSTEP Cycle Time ...
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Serial Port Timing nIOW nRTSx, nDTRx IRQx nCTSx, nDSRx, nDCDx IRQx nIOW IRQx nIOR nRIx t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx Inactive ...
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DATA IRRX nIRRX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width at 4.8kbaud t1 ...
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DATA IRTX nIRTX Parameter t1 Pulse Width at 115kbaud t1 Pulse Width at 57.6kbaud t1 Pulse Width at 38.4kbaud t1 Pulse Width at 19.2kbaud t1 Pulse Width at 9.6kbaud t1 Pulse Width at 4.8kbaud t1 ...
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DATA IRRX nIRRX t3 t4 MIRRX t5 t6 nMIRRX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated Output "On" Notes: ...
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DATA IRTX nIRTX t3 t4 MIRTX t5 t6 nMIRTX Parameter t1 Modulated Output Bit Time t2 Off Bit Time t3 Modulated Output "On" t4 Modulated Output "Off" t5 Modulated Output "On" t6 Modulated Output "On" Notes: ...
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Parallel Port Timing PD0- PD7 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN PINTR (SPP) nACK PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR t1 nINIT, nSTROBE, nAUTOFD Delay from nIOW Inactive t2 PINTR Delay from nACK, nFAULT t3 PINTR Active ...
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Parallel Port EPP Timing AX SD<7:0> t17 t8 nIOW IOCHRDY t13 t20 nWRITE t1 PD<7:0> nDATAST nADDRSTB nWAIT Parameter t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change t3 nWRITE to Command Asserted t4 nWAIT Deasserted to ...
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AX t19 IOR SD<7:0> t8 IOCHRDY t9 t21 nWRITE t2 t25 PD<7:0> DATASTB ADDRSTB nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 16 - EPP 1.9 DATA OR ADDRESS READ ...
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PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t6 PDATA Hi-Z to nWAIT Deasserted t7 PDATA Valid to ...
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AX SD<7:0> t17 nIOW t8 IOCHRDY nWRITE PD<7:0> nDATAST nADDRSTB nWAIT Parameter t1 nIOW Asserted to PDATA Valid t2 Command Dessserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command Deasserted t5 Command Deasserted to PDATA Invalid ...
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AX t19 nIOR SD<7:0> t8 IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT nIOR Deasserted to Command Deasserted t2 nWAIT Asserted to IOCHRDY Deasserted t3 Command Deasserted to PDATA Hi-Z t4 Command Asserted to PDATA Valid t5 nIOR Asserted to IOCHRDY ...
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Parallel Port ECP Timing Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500 Kbps allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next ...
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Output Drivers To facilitate higher performance data transfer, the use of balanced CMOS active drivers for critical signals (Data, HostAck, HostClk, PeriphAck, PeriphClk) are used ECP Mode. Because the use of active drivers can present compatibility problems in Compatible Mode ...
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PDATA<7:0> nSTROBE BUSY t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed t4 nBUSY Deasserted to PDATA Changed t5 nSTROBE Asserted to BUSY Asserted t6 nSTROBE Deasserted to Busy Deasserted ...
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PDATA<7:0> nACK nAUTOFD t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted t4 nACK Deasserted to nAUTOFD Asserted t5 nAUTOFD Asserted to nACK Asserted t6 nAUTOFD Deasserted to nACK Deasserted NOTES: ...
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Package Outlines 0. -C- Notes: 1 Coplanarity is 0.100mm maximum. 2 Tolerance on the position of the leads is 0.13mm maximum. 3 Package body dimensions D1 and E1 do not include the ...
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ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...