LPC47M172_07 SMSC [SMSC Corporation], LPC47M172_07 Datasheet

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LPC47M172_07

Manufacturer Part Number
LPC47M172_07
Description
Advanced I/O Controller with Motherboard GLUE Logic
Manufacturer
SMSC [SMSC Corporation]
Datasheet
Product Features
SMSC LPC47M172
3.3V Operation (5V tolerant)
LPC Interface
− Multiplexed Command, Address and Data Bus
− Serial IRQ Interface Compatible with Serialized IRQ
ACPI 1.0b/2.0 Compliant
Programmable Wake-up Event Interface
PC99a/PC2001 Compliant
General Purpose Input/Output Pins (13)
Fan Tachometer Inputs (2)
Green and Yellow Power LEDs
ISA Plug-and-Play Compatible Register Set
Motherboard GLUE Logic
− 5V Reference Generation
− 5V Standby Reference Generation
− IDE Reset/Buffered PCI Reset Outputs
− Power OK Signal Generation
− Power Sequencing
− Power Supply Turn On Circuitry
− Resume Reset Signal Generation
− Hard Drive Front Panel LED
− Voltage Translation for DDC to VGA Monitor
− SMBus Isolation Circuitry
− CNR Dynamic Down Control
2.88MB Super I/O Floppy Disk Controller
− Licensed CMOS 765B Floppy Disk Controller
− Software and Register Compatible with SMSC's
− Supports One Floppy Drive
− Configurable Open Drain/Push-Pull Output Drivers
− Supports Vertical Recording Format
16-Byte Data FIFO
− 100% IBM Compatibility
− Detects All Overrun and Underrun Conditions
Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
− DMA Enable Logic
− Data Rate and Drive Control Registers
480 Address, Up to Eight IRQ and Three DMA
Options
Support for PCI Systems
Proprietary 82077AA Compatible Core
DATASHEET
LPC47M172
Advanced I/O Controller
with Motherboard GLUE
Logic
Enhanced Digital Data Separator
− 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps
− Programmable Precompensation Modes
Keyboard Controller
− 8042 Software Compatible
− 8 Bit Microcomputer
− 2k Bytes of Program ROM
− 256 Bytes of Data RAM
− Four Open Drain Outputs Dedicated for
− Asynchronous Access to Two Data Registers and
− Supports Interrupt and Polling Access
− 8 Bit Counter Timer
− Port 92 Support
− Fast Gate A20 and KRESET Outputs
Serial Ports
− Two Full Function Serial Ports
− High Speed 16C550A Compatible UART with
− Supports 230k and 460k Baud
− Programmable Baud Rate Generator
− Modem Control Circuitry
− 480 Address and 15 IRQ Options
Infrared Port
− Multiprotocol Infrared Interface
− 32-Byte Data FIFO
− IrDA 1.0 Compliant
− SHARP ASK IR
− HP-SIR
− 480 Address, Up to 15 IRQ and Three DMA Options
Multi-Mode Parallel Port with ChiProtect
− Standard Mode IBM PC/XT
− Enhanced Parallel Port (EPP) Compatible - EPP 1.7
− IEEE 1284 Compliant Enhanced Capabilities Port
− ChiProtect Circuitry for Protection
− 960 Address, Up to 15 IRQ and Three DMA Options
Interrupt Generating Registers
− Registers Generate IRQ1 – IRQ15 on Serial IRQ
XOR-Chain Board Test
128 Pin MQFP Lead-free RoHS Compliant
Package, 3.2 mm Footprint
Data Rates
Keyboard/Mouse Interface
One Status Register
Send/Receive 16-Byte FIFOs
Compatible Bi-directional Parallel Port
and EPP 1.9 (IEEE 1284 Compliant)
(ECP)
Interface.
SMSC/Non-SMSC Register Sets (Rev. 01-11-07)
,
PC/AT, and PS/2
Datasheet

Related parts for LPC47M172_07

LPC47M172_07 Summary of contents

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Product Features 3.3V Operation (5V tolerant) LPC Interface − Multiplexed Command, Address and Data Bus − Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems ACPI 1.0b/2.0 Compliant Programmable Wake-up Event Interface PC99a/PC2001 Compliant General Purpose Input/Output Pins ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet LPC47M172-NW for 128 Pin, MQFP lead-free RoHS compliant package (3.2mm footprint) 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. ...

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Table Of Contents Chapter 1 General Description.............................................................................................................. 11 Chapter 2 Pin Layout ............................................................................................................................ 12 Chapter 3 Description of Pin Functions ................................................................................................ 14 3.1 Buffer Name Descriptions ..........................................................................................................................22 3.2 Pins With Internal Resistors .......................................................................................................................23 3.3 Pins That Require External Resistors.........................................................................................................23 3.4 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.9 Result Phase..............................................................................................................................................53 6.10 Command Set/Descriptions ....................................................................................................................53 6.10.1 Instruction Set..................................................................................................................................56 6.11 Data Transfer Commands ......................................................................................................................62 6.11.1 Read Data .......................................................................................................................................62 6.12 Read Deleted Data .................................................................................................................................63 6.13 Read A Track..........................................................................................................................................64 6.14 Write Data...............................................................................................................................................65 6.15 ...

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EPP 1.9 Read ............................................................................................................................................95 7.8 EPP 1.7 Operation .....................................................................................................................................95 7.8.1 Software Constraints...........................................................................................................................95 7.9 EPP 1.7 Write.............................................................................................................................................96 7.10 EPP 1.7 Read .........................................................................................................................................96 7.10.1 Extended Capabilities Parallel Port .................................................................................................97 7.10.2 Vocabulary.......................................................................................................................................97 7.11 ECP Implementation Standard ...............................................................................................................98 7.11.1 Description.......................................................................................................................................98 7.12 Register Definitions.................................................................................................................................99 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.25.15 Memory Configurations .................................................................................................................117 7.25.16 Register Definitions .......................................................................................................................117 7.25.17 External Clock Signal ....................................................................................................................118 7.25.18 Default Reset Conditions ...............................................................................................................118 7.25.19 GateA20 and Keyboard Reset.......................................................................................................118 7.26 Port 92 Fast Gatea20 and Keyboard Reset..........................................................................................118 7.26.1 ...

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Chapter 13 Timing Diagrams ................................................................................................................202 13.1 ECP Parallel Port Timing ......................................................................................................................211 13.1.1 Parallel Port FIFO (Mode 101).......................................................................................................211 13.1.2 ECP Parallel Port Timing ...............................................................................................................211 13.1.3 Forward-Idle ..................................................................................................................................211 13.1.4 Forward Data Transfer Phase .......................................................................................................211 13.1.5 Reverse-Idle Phase .......................................................................................................................211 13.1.6 Reverse Data Transfer ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Figure 13.22 - Keyboard/Mouse Receive/Send Data Timing .....................................................................................216 Figure 13.23 - Fan Tachometer Input Timing .............................................................................................................217 Figure 13.24 - Power Led Output Timing ...................................................................................................................217 Figure 13.25 - REF5V/REF5V_STBY Output When VCC/VTR Ramps ...

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Table 7.10 - I/O Address Map ....................................................................................................................................114 Table 7.11 - Host Interface Flags ...............................................................................................................................115 Table 7.12 - Status Register ......................................................................................................................................117 Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................118 Table 7.14 - Keyboard Port 92 Register.....................................................................................................................119 Table 7.15 - ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers .................................193 Table 12.1 - Operational DC Characteristics..............................................................................................................195 Table 12.2 - S3-S5 Standby Current ..........................................................................................................................200 Table 13.1 - nIDE_RSTDRV Timing...........................................................................................................................220 Table 13.2 ...

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Chapter 1 General Description The LPC47M172 is a 3.3V (5V tolerant) PC99a/PC2001 compliant Advanced I/O controller for Desktop PCs. The device, which implements the Low Pin Count (LPC) interface, includes I/O functionality as well as Motherboard GLUE logic into a ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 2 Pin Layout MCLK 1 MDAT 2 KCLK 3 KDAT 4 GA20M 5 VCC 6 nKBDRST 7 VSS 8 nDSKCHG 9 nHDSEL 10 nRDATA 11 nWRTPRT 12 nTRK0 13 nWGATE 14 ...

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Note: Pin 117 is used to select the mode of the logical device numbering. This pin affects the LD_NUM bit in the TEST 7 register (configuration register 0x29), which is used to select logical device numbering in the LPC47M172. See ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 3 Description of Pin Functions NAME PIN# (NOTE 1) 6,31, VCC +3.3 Volt Main Supply Voltage (5) 49,60, 123 76,93, VTR +3.3 Volt Standby Supply Voltage (4) Note 107, 117 See ...

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NAME PIN# (NOTE 1) 63 nPCI_RESET Active low input used as LPC Interface Reset. 3.3V and 5V buffered copy of PCI Reset signal is available on nPCIRST_OUT and nIDE_RSTDRV. These pins are listed under GLUE PINS. 99 nIO_PME Power Management ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME PIN# (NOTE 1) 16 nSTEP Step Pulse Output. This active low high current driver issues a low pulse for each track-to-track movement of the head. Can be configured as an Open-Drain ...

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NAME PIN# (NOTE 1) 26 nRTS1 Active low Request to Send output for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME PIN# (NOTE 1) 121 nDSR2 Active low Data Set Ready input for serial port 2. See description for nDSR1. 122 nRTS2 Active low Request to Send output for Serial Port 2. ...

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NAME PIN# (NOTE 1) 45 nERROR A low on this input from the printer indicates that there is an error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME PIN# (NOTE 1) 73 nPCIRST_OUT Buffered PCI Reset Output 74 nPCIRST_OUT Second Buffered PCI Reset Output 2 75 nFPRST Reset Input from Front Panel 77 nBACKFEED_ Open-Drain Output used for STR ...

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NAME PIN# (NOTE 1) 106, GP13-GP15 General Purpose I/O. GPIO can be 108, configured as an open-drain output. 109 111 GP16/ General Purpose I/O. GPIO can be configured as an open-drain output. Fan Tachometer 1 Input FAN_TACH1 112 GP17/ General ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet time the pin will reflect the state of the transmit output of the Serial Port 2 block. This is a VCC powered pin. Note 10: These pins are internally pulled down to ...

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Pins With Internal Resistors The following pins have internal resistors: SIGNAL NAME nCPU_PRESENT nFPRST nPRIMARY_HD PWRGD_PS nSCSI nSECONDARY_HD TEST_EN 3.3 Pins That Require External Resistors The following pins require external resistors: Table 3.3 - Pins that Require External Resistors ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet SIGNAL NAME nIDE_RSTDRV nPS_ON nBACKFEED_CUT SCK_BJT_GATE nCDC_DWN_ENAB YLW_LED nHD_LED DDCSDA_3V DDCSCL_3V DDCSDA_5V DDCSCL_5V SMB_CLK_M SMB_CLK_R SMB_DAT_M SMB_DAT_R GRN_LED GPIOs 3.4 Default State of Pins The following table shows the default state of ...

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SIGNAL NAME PWR WELL REF5V_STBY VTR REF5V VCC CLOCKI VCC CLOCKI32 VTR nIO_PME VTR PCI_CLK VCC nLPCPD VCC nPCI_RESET VCC SER_IRQ VCC nLDRQ VCC nLFRAME VCC LAD[0:3] VCC nDSKCHG VCC nHDSEL VCC nRDATA VCC nWRTPRT VCC nTRK0 VCC nWGATE VCC ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet SIGNAL NAME PWR WELL nCTS2 VCC nDTR2 VCC nRI2 VTR IRRX2 VCC IRTX2 VCC SLCT VCC PE VCC BUSY VCC nACK VCC PD[7:0] VCC ERROR VCC nSLCTIN VCC nINITP VCC nALF VCC ...

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SIGNAL NAME PWR WELL nSLP_S3 VTR nSLP_S5 VTR nRSMRST VTR PWRGD_3V VTR nPCIRST_OUT VTR nPCIRST_OUT2 VTR GP10-GP15 VTR GP16 VTR FAN_TACH1 GP17 VTR FAN_TACH2 SMB_CLK_M VTR SMB_CLK_R VTR SMB_DAT_M VTR SMB_DAT_R VTR DDCSDA_5V VTR GP20 DDCSCL_5V VTR GP21 DDCSDA_3V VTR ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 4 Block Diagram SER_IRQ SERIAL IRQ / Interrupt PCI_CLK Generating Registers LAD[3:0] nLFRAME LPC nLDRQ Bus Interface nPCI_RESET nLPCPD PME / nIO_PME Power Control GP10-GP15, GP16*, GP17* (GP20-GP23)* GPIOs GP24* F_CAP ...

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Chapter 5 Power and Clock Functionality The LPC47M172 has three power planes: VCC, VTR and V5P0_STBY. 5.1 3 Volt Operation / 5 Volt Tolerance The LPC47M172 is a 3.3 Volt part intended solely for 3.3V applications. Non-LPC bus ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 5.3.1 Trickle Power Functionality When the LPC47M172 is running under VTR only (VCC removed), PME wakeup events are active and (if enabled) able to assert the nIO_PME pin active low. The following ...

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Bit 0 controls the source of the 32kHz (nominal) clock for the nFPRST debounce circuitry, the LED blink logic and the “wake on specific key” logic. When the external 32kHz clock is connected, that will be the source for the ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 6 Functional Description The following sections describe the functional blocks located in the LPC47M172 (see Figure 4.1). The various Super I/O components are described in the following sections and their registers ...

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Host Processor Interface (LPC) The host processor communicates with the LPC47M172 through a series of read/write registers via the LPC interface. The port addresses for these registers are shown in Table 6.1. Register access is accomplished through I/O cycles ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.3.4 NLFRAME Usage nLFRAME is used by the host to indicate the start of cycles and the termination of cycles due to an abort or time-out condition. This signal ...

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Power Management CLOCKRUN Protocol The CLKRUN# pin is not implemented in the LPC47M172. See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.1. LPCPD Protocol See the “Low Pin Count (LPC) Interface Specification” Revision 1.0, Section 8.2. ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet SYNC Error Indication The LPC47M172 reports errors via the LAD[3:0] = 1010 SYNC encoding. If the host was reading data from the LPC47M172, data will still be transferred in the next two ...

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Floppy Disk Controller The Floppy Disk controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital data Separator, Write Precompensation and Data Rate Selection logic for ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.4.3 Status Register A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the internal interrupt signal and several disk interface pins in PS/2 and Model 30 ...

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BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic “1” indicates that the disk is write protected. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 3 HEAD SELECT ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this ...

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Digital Output Register (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also contains the enable for the DMA logic and a software reset bit. The contents of the ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.4 - Internal 2 Drive Decode - Drives 0 and 1 Swapped DIGITAL OUTPUT REGISTER Bit 5 Bit 4 Bit1 BIT 6 ...

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DIGITAL OUTPUT REGISTER Bit Note: L0-CRF2-Bx = FDC Logical Device, Configuration Register F2, Bit x. 6.4.7 Data Rate Select Register (DSR) Address 3F4 WRITE ONLY This register is write only used to program ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 5 UNDEFINED Should be written as a logic “0”. BIT 6 LOW POWER A logic “1” written to this bit will put the floppy controller into manual low power mode. The ...

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DT1 DT0 0 0 DRATE0 1 0 DRATE0 0 1 DRATE0 1 1 DRATE1 Table 6.10 - Default Precompensation Delays 6.4.8 Main Status Register Address 3F4 READ ONLY The Main Status Register is a read-only register and indicates the status ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.4.9 Data Register (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data ...

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Digital Input Register (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 DSK CHG RESET N/A COND. BIT 0 – 6 UNDEFINED The data bus outputs D0 – 6 are read as ‘0’. ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BITS 0 – 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 6.8 for the settings corresponding to the individual data rates. The data rate ...

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BIT 3 – 7 RESERVED Should be set to a logical “0” Table 6.9 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT NO. SYMBOL BIT NO. SYMBOL BIT NO. SYMBOL ...

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RESET There are three sources of system reset on the FDC: the nPCI_RESET pin, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.7 Controller Phases For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. 6.7.1 Command Phase After ...

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DMA Mode - Transfers from the FIFO to the Host The FDC generates a DMA request cycle when the FIFO contains (16 - <threshold>) bytes, or the last byte of a full sector transfer has been placed in the FIFO. ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.16 - Description of Command Symbols SYMBOL NAME C Cylinder Address The currently selected address 255. D Data Pattern D0, D1 Drive Select 0-1 DIR Direction Control DS0, DS1 ...

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SYMBOL NAME N Sector Size Code This specifies the number of bytes in a sector. If this parameter is NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.10.1 Instruction Set PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command ...

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PHASE R/W D7 Command W MT MFM Execution Result PHASE R/W D7 Command W MT MFM ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PHASE R/W D7 Command Execution Result PHASE R/W D7 Command W MT MFM W ...

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PHASE R/W D7 Command W 0 Result R 1 PHASE R/W D7 Command Execution for W Each Sector Repeat Result PHASE R/W ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PHASE R/W D7 Command Result R PHASE R/W D7 Command Execution PHASE R/W D7 Command Execution W ...

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PHASE R/W D7 Command Execution Result PHASE R/W D7 Command PHASE R/W D7 Command W Result R PHASE R/W D7 Command W LOCK Result R SC ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.11 Data Transfer Commands All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding ...

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At the completion of the Read Data command, the head is not unloaded until after the Head Unload Time Interval (specified in the Specify command) has elapsed. If the host issues another command before the head unloads, then the head ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.21 - Skip Bit vs. Read Deleted Data Command DATA ADDRESS MARK TYPE SK BIT ENCOUNTERED VALUE 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data 6.13 Read ...

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Write Data After the Write Data command has been issued, the FDC loads the head ( the unloaded state), waits the specified head load time if unloaded (defined in the Specify command), and begins reading ID ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 6.23 - Verify Command Result Phase Table DTL 0 0 EOT <= # Sectors Per Side SC = DTL 0 0 EOT > # Sectors Per Side ...

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GAP4a SYNC IAM GAP1 80x 12x 50x SYSTEM 3740 (SINGLE DENSITY) FORMAT GAP4a SYNC IAM GAP1 40x 6x 26x GAP4a SYNC IAM GAP1 80x 12x 50x ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.18 Control Commands Control commands differ from the other commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control ...

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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1. Seek command - Step to the proper track 2. Sense Interrupt Status command - Terminate the Seek command 3. Read ID - ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.20 Sense Drive Status Sense Drive Status obtains drive status information. It has not execution phase and goes directly to the result phase from the command phase. Status Register 3 contains the ...

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PRETRK - Pre-Compensation Set to Track 0 EIS - Enable Implied Seek. When set to "1", the FDC will perform a Seek operation before executing a read or write command. Defaults to no implied seek. EFIFO - A "1" disables ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet that it is working in an “extended track area” (greater than 255). Any command issued will use the current PCN value except for the Recalibrate command, which only looks for the TRACK0 ...

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The perpendicular mode command is enhanced to allow specific drives to be designated Perpendicular recording drives. This enhancement allows data transfers between Conventional and Perpendicular drives without having to issue Perpendicular mode commands between the accesses of the different drive ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.27 Enhanced DUMPREG The DUMPREG command is designed to support system run-time diagnostics and application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth ...

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DLAB *Note: DLAB is Bit 7 of the Line Control Register The following section describes the operation of the registers. 6.28.2 Receive Buffer Register (RB) Address Offset = 0H, DLAB = 0, READ ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Bit 3 This bit enables the MODEM Status Interrupt when set to logic “1”. This is caused when one of the Modem Status Register bits changes state. Bits 4 through 7 These ...

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Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in the Interrupt Identification Register (refer to Interrupt Control Table). When the CPU accesses the IIR, the Serial Port freezes all interrupts and indicates ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER 6.28.7 Line Control Register (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This ...

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Note: The receiver will ignore all stop bits beyond the first, regardless of the number used in transmitting. Bit 3 Parity Enable bit. When bit logic “1”, a parity bit is generated (transmit data) or checked (receive ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Bit 2 This bit controls the Output 1 (OUT1) bit. This bit does not have an output pin and can only be read or written by the CPU. Bit 3 Output 2 ...

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FIFO it applies to. associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not have a valid stop bit. Bit ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data ...

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If a two is loaded the output is a divide by 2 signal with a 50% duty cycle greater is loaded the output is low for ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 6.29.3 FIFO Polled Mode Operation With FCR bit 0 = “1” resetting IER bits all to zero puts the UART in the FIFO Polled Mode of ...

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REGISTER/SIGNAL Interrupt Enable Register Interrupt Identification Reg. FIFO Control Line Control Reg. MODEM Control Reg. Line Status Reg. MODEM Status Reg. TXD1, TXD2 INTRPT (RCVR errs) INTRPT (RCVR Data Ready) INTRPT (THRE) OUT2B RTSB DTRB OUT1B RCVR FIFO XMIT FIFO ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 32 - Register Summary for an Individual UART Channel REGISTER REGISTER NAME ADDRESS (Note 1) ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding ...

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DLAB is Bit 7 of the Line Control Register (ADDR = 3). Note 1 Bit 0 is the least significant bit the first bit serially transmitted or received. Note 2 When operating in the XT mode, this bit ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 7 Notes On Serial Port Operation 7.1 FIFO Mode Operation: 7.1.1 General The RCVR FIFO will hold bytes regardless of which trigger level is selected. 7.1.2 TX and ...

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Infrared Interface The infrared interface provides a two-way wireless communications port using infrared as a transmission medium. Several IR implementations have been provided for the second UART in this chip, IrDA, HP-SIR and Amplitude Shift Keyed IR. The IR ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet The Parallel Port configuration registers are summarized in Table 11.2 in the “Configuration” section. The Parallel Port logical device configuration registers (0xF0 and 0xF1) are defined in Table 11.11. The parallel port ...

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Table 7.1 - Parallel Port Connector HOST SMSC CONNECTOR PIN NUMBER 1 See Chapter 3 Description of Pin 2-9 Functions (1) = Compatible Mode (3) = High Speed Mode Note: For the ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Parallel Port Mode Register 2, 0xF1 in Serial Port Logical Device Configuration Registers) is ‘1’, the TMOUT bit is cleared on the trailing edge of a read of the EPP Status Register. ...

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BIT 4 IRQE - INTERRUPT REQUEST ENABLE The interrupt request enable bit when set to a high level may be used to enable interrupt requests from the Parallel Port to the CPU. An interrupt request is generated on the IRQ ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.4.8 EPP Data Port 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of ‘07H’ from the base address. Refer to EPP DATA PORT 0 for ...

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The chip latches the data from the internal data bus for the PData bus and drives the sync that indicates that no more wait states are required followed by the TAR to complete the write cycle. 7. Peripheral asserts ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.9 EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. The chip inserts wait states into the ...

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EPP SIGNAL EPP NAME nWAIT nWait nDATASTB nData Strobe nRESET nReset nADDRSTB Address Strobe PE Paper End SLCT Printer Selected Status nERR Error Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet nReverseRequest, nInit nAckReverse, PError Xflag, Select ECPMode, nSelectln HostClk, nStrobe Reference Document: IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev 1.14, July 14, 1993. This document is available from ...

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Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support for compression is optional. NAME TYPE nStrobe O PData 7:0 I/O nAck I PeriphAck (Busy) I ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME ADDRESS (Note 1) data +000h R/W ecpAFifo +000h R/W dsr +001h R/W dcr +002h R/W cFifo +400h R/W ecpDFifo +400h R/W tFifo +400h R/W cnfgA +400h R cnfgB +401h R/W ecr ...

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Device Status Register (dsr) ADDRESS OFFSET = 01H The Status Port is located at an offset of ‘01H’ from the base address. Bits0 - 2 are not implemented as register bits, during a read of the Printer Status Register ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of the state of this bit. In all other modes, Direction is valid ...

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The readIntrThreshold can be determined by setting the direction bit to 1 and filling the empty tFIFO a byte at a time until serviceIntr is set. This may generate a spurious interrupt, but will indicate that the threshold has been ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet BIT 4 nErrIntrEn Read/Write (Valid only in ECP Mode) 1: Disables the interrupt generated on the asserting edge of nFault. 0: Enables an interrupt pulse on the high to low edge of ...

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R/W 000: Standard Parallel Port Mode . In this mode the FIFO is reset and common drain drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will not tri-state the output drivers in ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.13 Operation 7.13.1 Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic ...

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Termination from ECP Mode Termination from ECP Mode is similar to the termination from Nibble/Byte Modes. The host is permitted to terminate from ECP Mode only in specific well-defined states. The termination can only be executed while the bus ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.19 LPC Connections The interface can never stall causing the host to hang. The width of data transfers is strictly controlled on an I/O address basis per this specification. All FIFO-DMA transfers ...

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DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA services. To use the DMA transfers, the host first sets up the direction and state as in the programmed ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet An interrupt is generated when serviceIntr is 0 and the number of bytes in the FIFO is greater than or equal to (16-<threshold>). (If the threshold = 12, then the interrupt is ...

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Note 1: Start Frame pulse can be 4-8 clocks wide depending on the location of the device in the PCI bridge hierarchy in a synchronous bridge design. B) Stop Frame Timing with Host using 17 SER_IRQ sampling period IRQ14 FRAME ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.23.3 SER_IRQ Data Frame Once a Start Frame has been initiated, the LPC47M172 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames from there. Each IRQ/Data ...

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Latency Latency for IRQ/Data updates over the SER_IRQ bus in bridge-less systems with the minimum Host supported IRQ/Data Frames of seventeen, will range clocks (3.84μS with a 25MHz PCI Bus or 2.88uS with a 33MHz PCI ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.25 8042 Keyboard Controller Description The LPC47M172 is a Super I/O and Universal Keyboard Controller that is designed for intelligent keyboard management in desktop computer applications. The Universal Keyboard Controller uses an ...

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Keyboard Data Write This bit write only register. When written, the C/D status bit of the status register is cleared to zero and the IBF bit is set. 7.25.3 Keyboard Data Read This ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.25.9 MIRQ If “EN FLAGS” has been executed and P25 is set to a one:; IBF is inverted and gated onto MIRQ. The MIRQ signal can be connected to system interrupt to ...

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Interrupts The LPC47M172 provides the two 8042 interrupts: IBF and the Timer/Counter Overflow. 7.25.15 Memory Configurations The LPC47M172 provides 2K of on-chip ROM and 256 bytes of on-chip RAM. 7.25.16 Register Definitions Host I/F Data Register The Input Data ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.25.17 External Clock Signal The LPC47M172 Keyboard Controller clock source MHz clock generated from a 14.318 MHz clock. The reset pulse must last for at least 24 16 MHz ...

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BIT 7 ALT_A20 Signal control. Writing this bit causes the ALT_A20 signal to be driven low. Writing this bit causes the ALT_A20 signal to be driven high. 0 Alternate ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 8042 P20 P92 Bit 0 Note: When Port 92 is disabled, writes are ignored and reads return undefined values. Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M ...

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The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Keyboard Logical Device at 0xF0. SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic KLATCH Bit VCC D Q KINT CLR RD 60 Figure 7.2 - ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet These bits are defined as follows: Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched MINT (default), 1=MINT is the latched 8042 MINT. Bit[3]: KLATCH ...

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Bit[5] K_ISO. Enables/disables isolation of keyboard signals into 8042. Does not affect the KDAT signal to the keyboard wakeup (PME) logic. 1=block keyboard clock and data signals into 8042 0= do not block keyboard clock and data signals into 8042 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet I/O and can be individually enabled to generate a PME (except GP24). GPIOs must be programmed as inputs to generate a PME. 7.27.1 GPIO Pins The Table 7.16 summarizes the GPIO functionality, ...

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Table 7.17 - General Purpose I/O Port Assignments DEFAULT ALT. FUNC. 1 FUNCTION nCDC_DWN_ENAB GP24 GP10 GP11 GP12 GP13 GP14 GP15 GP16 FAN_TACH1 GP17 FAN_TACH2 DDCSDA_5V GP20 DDCSCL_5V GP21 DDCSDA_3V GP22 DDCSCL_3V GP23 Reserved Note 1: The GPIO Data and ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.27.4 GPIO Operation The operation of the GPIO ports is illustrated in Figure 7.4. D-TYPE SD-bit D Q GPx_nIOW Transparen GPx_nIOR GPIO Data Register Bit-n Note: Figure 7.4 is ...

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GPIO PME Functionality The LPC47M172 provides 12 GPIOs that can directly generate a PME. See the Table 7.16. The polarity bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet The PME functionality is controlled by the PME status and enable registers in the Power Control/Runtime Register block, which is located at the address programmed in configuration registers 0x60 and 0x61 in ...

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BIT The timing for the keyboard clock and data signals are shown in the “Timing Diagrams” section. The process to find a match for the scan code stored in the Keyboard Scan ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.29.1 Fan Tachometer Inputs A fan tachometer input is used to measure the speed at which a fan is rotating. The fan tachometer input is a train of square pulses with a ...

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The internal count register does rollover, however, and continuously counts to FFFFh as long as the fan is stalled. In the event the counter reaches FFFFh, the PME status bit is set and the count ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet SMSC I/O 7.30.2 Yellow and Green Power LED Pins NAME GRN_LED YLW_LED nSLP_S5 Note: The LEDs require external pull-up to VTR. The green and yellow LED outputs are controlled by the LED ...

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INPUTS nSLP_S5 GRN_YLW Bit Notes: *** Default state The LED the Hi-Z state. The LED is blinking at 0. the 0.67 Hz state. The 32.768 kHz clock input is used to ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.31.2 5V Main Reference Generation REF5V is used to help power-up various system components’ 5V tolerant buffers. This signal is used to guarantee there are no power sequencing requirements at each particular ...

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Note: The maximum voltage drop across the diode is 350mV. 7.31.4 Reference Timings See Figure 13.25 to Figure 13.28 in the “Timing Diagrams” section. 7.32 IDE Reset Output Pin nIDE_RST is an open drain buffered copy of nPCI_RESET. This signal ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME nPCIRST_OUT nPCIRST_OUT2 Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table INPUT nPCI_RESET 0 1 See Table 13.2 for nPCI_RSTOUT and nPCI_RSTOUT2 timings. 7.34 Voltage Translation Circuit Table 7.31 - Voltage Translation ...

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Note: If any of the Alternate Function Select bits in GP20 to GP23 registers are set for DDC function, the DDC functions will be selected on all four GP20 to GP23 pins. However recommended that the DDC functions ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 4.7k DDCSDA_3V MCH DDCSCL_3V NOTE: The switch is implemented as an n-channel switch that will not pass a full voltage swing. It provides a current path to ground. The board designer should ...

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PWRGD_PS SMB_CLK_M 0 Don’t Care 1 1 3.6V (max) PWRGD_PS SMB_DAT_M 0 Don’t Care 3.6V (max) 2.7k SMB_CLK_M ICH, CNR, DIMMS, SMB_DAT_M CLK GEN PWRGD_PS NOTE: The switch is implemented as an n-channel switch that will not ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.36 PS_ON Logic Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins NAME nPS_ON nCPU_PRESENT nSLP_S3 The nPS_ON is a function of nSLP_S3 and nCPU_PRESENT according to the truth table below. The nCPU_PRESENT ...

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Note: The actual minimum debounce time is 15.8msec See Table 13.5 for PWRGD_3V timing. nFPRST The following figure shows the discrete implementation for the creation of the PWRGD_3V signal on the motherboard. nFPRST PWRGD_PS Figure 7.12 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Press nFPRST (before debounce) Internal nFPRST (after debounce) 7.38 SCK_BJT_GATE Output NAME SCK_BJT_GATE Note: The SCK_BJT_GATE requires external pull-up to V_5P0_STBY. The SCK_BJT_GATE pin is an open drain output that provides the ...

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MCH SMSC I/O See Table 13.4 for SCK_BJT_GATE timing. 7.39 Backfeed Cut and Latched Backfeed Cut Circuitry Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins Name nBACKFEED_CUT LATCHED_BF_CUT Note: The nBACKFEED_CUT requires an external pull-up to V_5P0_STBY. nBACKFEED_CUT is a signal ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PWRGD_PS nSLP_S3 nSLP_S5 Figure 7.16 - Backfeed Cut and Latched Backfeed Cut Circuit The LATCHED_BF_CUT is generated from nBACKFEED_CUT and nSLP_S5 powered by VTR. Table 7.45 - LATCHED_BF_CUT Truth Table ...

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The t1 and t2 values are guaranteed by the inherent design of the system and are not controlled by the LPC47M172. V_5P0_STBY nSLP_S3 PWRGD_PS nBACKFEED_CUT nSLP_S5 LATCHED_BF_CUT Figure 7.17 - Latched Backfeed Cut Power Up Sequence Table 7.46 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet The second possible sequence, shown in the figure below normal powerdown sequence. The nBACKFEED_CUT signal goes from low to high when nSLP_S3 goes low, and nSLP_S5 goes from high to ...

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The following figure shows a flowchart of the logic. Start of Suspend Power Up Sequence nBACKFEED_CUT = 0 nSLP_S5 = 0 LATCHED_BF_CUT = 0 No nBACKFEED_CUT = 1? Yes Power Rails Stabilized? (Period T2) (Verified by ICH) No Yes nSLP_S5 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 7.40 Resume Reset Logic NAME nRSMRST V_5P0_STBY The nRSMRST signal is the reset output for the ICH resume well. This signal is used as a power on reset signal as well as ...

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NAUD_LNK_RST Note: If GP24 is programmed as GPIO output the GP data bit will also control nCDC_DWN_ENAB input to the CNR logic. This follows the boolean equation: (nAUD_LNK_RST)x( nCDC_DWN_ENAB )=nCDC_DWN_RST nAUD_LNK_RST See Table 13.6 for CNR ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 8 Power Control Runtime Registers Table 8.1 shows the runtime registers summary in the Power Control logical Device. Table 8.2 shows the runtime registers description in the Power Control logical device. ...

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Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 REG OFFSET NAME PME_STS Default = 0x00 on VTR POR N/A 0x01 – 0x03 PME_EN Default = 0x00 on VTR POR N/A 0x05 – 0x07 PME_STS3 Default = ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME PME_STS1 Default = 0x00 on VTR POR N/A PME_EN3 Default = 0x00 on VTR POR SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DESCRIPTION (Type) 0x0A PME Wake Status Register 1 This ...

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REG OFFSET NAME PME_EN2 Default = 0x00 on VTR POR PME_EN1 Default = 0x00 on VTR POR N/A LED Default = 0x03 on VTR POR SMSC LPC47M172 DESCRIPTION (Type) 0x0D PME Wake Enable Register 2 This register is used to ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME Keyboard Scan Code Default = 0x00 on VTR POR Tach1 LSB Default = 0x00 on VTR POR Tach1 MSB Default = 0x00 on VTR POR Tach2 LSB Default = ...

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REG OFFSET NAME Force Disk Change Default = 0x01 on VCC POR Floppy Data Rate Select Shadow UART1 FIFO Control Shadow INT_GEN1 Default = 0xFF on VCC POR and HARD RESET SMSC LPC47M172 DESCRIPTION (Type) 0x18 Force Disk Change Bit[0] ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME INT_GEN2 Default = 0xFF on VCC POR and HARD RESET UART2 FIFO Control Shadow N/A 0x1E-0x1F Note 1: These bits are R/W bit, but have no effect on circuit ...

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Chapter 9 GPIO Runtime Registers Table 9.1 shows the runtime registers summary in the GPIO logical Device. Table 9.2 shows the runtime registers description in the GPIO logical device. These registers can only be accessed when LD_NUM bit in the ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 REG OFFSET NAME GP10 Default = 0x01 on VTR POR GP11 Default = 0x01 on VTR POR GP12 Default = 0x01 on ...

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REG OFFSET NAME GP17 Default = 0x01 on VTR POR GP20 Default = 0x04 on VTR POR Note 1 GP21 Default = 0x04 on VTR POR Note 1 GP22 Default = 0x04 on VTR POR Note 1 GP23 Default = ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME GP24 Default = 0x05 on VTR POR N/A 0x0D-0x14 GP1 Default = 0x00 on VTR POR GP2 Default = 0x00 on VTR POR N/A 0x17-0x1F Note 1: The In/Out, ...

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Chapter 10 Runtime Register Block Runtime Registers Table 10.1 shows the runtime register summary. See Table 10.2 - Runtime Register Block Runtime Registers Description. The Runtime Register Block runtime registers can only be accessed when LD_NUM bit in the TEST ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REGISTER TYPE PCI RESET OFFSET (HEX R/W - 2D-34 R ...

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REG OFFSET NAME (Type) PME_STS3 0x08 (R/W) Default = 0x00 on VTR POR PME_STS2 0x09 Default = 0x00 (R/W) on VTR POR SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION PME Wake Status Register 3 This register indicates ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME (Type) PME_STS1 0x0A Default = 0x00 (R/W) on VTR POR N/A 0x0B (R) PME_EN3 0x0C Default = 0x00 (R/W) on VTR POR SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DESCRIPTION PME ...

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REG OFFSET NAME (Type) PME_EN2 0x0D Default = 0x00 (R/W) on VTR POR PME_EN1 0x0E Default = 0x00 (R/W) on VTR POR N/A 0x0F (R) SMSC LPC47M172 Advanced I/O Controller with Motherboard GLUE Logic DESCRIPTION PME Wake Enable Register 2 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME (Type) LED 0x10 Default = 0x03 on (R/W) VTR POR 0x11 Keyboard Scan Code (R/W) Default = 0x00 on VTR POR Tach1 LSB 0x12 Default = 0x00 on (R) ...

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REG OFFSET NAME (Type) MSC_STS 0x17 Default = 0x00 (R/W) on VTR POR Force Disk Change 0x18 Default = 0x01 on (R/W) VCC POR Floppy Data Rate 0x19 Select Shadow (R) UART1 FIFO 0x1A Control Shadow (R) SMSC LPC47M172 Advanced ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME (Type) INT_GEN1 0x1B Default = 0xFF (R/W) on VCC POR and HARD RESET INT_GEN2 0x1C Default = 0xFF (R/W) on VCC POR and HARD RESET N/A 0x1D-0x1F (R) UART2 ...

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REG OFFSET NAME (Type) GP11 0x21 Default = 0x01 (R/W) on VTR POR GP12 0x22 Default = 0x01 (R/W) on VTR POR GP13 0x23 Default = 0x01 (R/W) on VTR POR GP14 0x24 Default = 0x01 (R/W) on VTR POR ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REG OFFSET NAME (Type) GP17 0x27 Default = 0x01 (R/W) on VTR POR GP20 0x28 Default = 0x04 (R/W) on VTR POR Note 3 GP21 0x29 Default = 0x04 (R/W) on VTR ...

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REG OFFSET NAME (Type) GP23 0x2B (R/W) Default = 0x04 on VTR POR Note 3 GP24 0x2C Default = 0x05 (R/W) on VTR POR N/A 0x2D-0x34 (R) GP1 0x35 Default = 0x00 (R/W) on VTR POR GP2 0x36 Default = ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Chapter 11 Configuration The Configuration of the LPC47M172 is very flexible and is based on the configuration architecture implemented in typical Plug-and-Play components. The LPC47M172 is designed for motherboard applications in which ...

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Configuration Sequence To program the configuration registers, the following sequence must be followed: 1. Enter Configuration Mode 2. Configure the Configuration Registers 3. Exit Configuration Mode. 11.1.5 Enter Configuration Mode To place the chip into the Configuration State the ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 11.1.8 Programming Example The following is an example of a configuration program in Intel 8086 assembly language. ;-------------------------------------------------. ; ENTER CONFIGURATION MODE | ;-------------------------------------------------‘ MOV DX,02EH MOV AX,055H OUT DX,AL ;-----------------------------------------------. ; ...

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Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x14 0x21 R 0x04 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x2E ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet INDEX TYPE PCI RESET 0xF8 R/W 0x08 LOGICAL DEVICE 2 CONFIGURATION REGISTERS (Serial Port 2) 0x30 R/W 0x00 0x60 R/W 0x00 0x61 R/W 0x00 0x70 0x00 R/W 0xF0 R/W 0x00 0xF1 R/W ...

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Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1 INDEX TYPE PCI RESET 0x02 W 0x00 0x03 R - 0x07 R/W 0x00 0x20 R 0x14 0x21 R 0x04 0x22 R/W 0x00 0x23 R - 0x24 R/W 0x44 0x26 R/W 0x2E 0x27 ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet INDEX TYPE PCI RESET LOGICAL DEVICE 3 CONFIGURATION REGISTERS (Parallel Port) 0x30 R/W 0x00 0x60 R/W 0x00 0x61 R/W 0x00 0x70 R/W 0x00 0x74 R/W 0x04 0xF0 R/W 0x3C 0xF1 R/W 0x00 ...

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Chip Level (Global) Control/Configuration Registers[0x00-0x2F] The chip-level (global) registers lie in the address range [0x00-0x2F]. The design MUST use all 8 bits of the ADDRESS Port for register selection. All unimplemented registers and bits ignore writes and return zero ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REGISTER PowerControl Default = 0x00 on VCC POR, VTR POR, SOFT RESET and HARD RESET OSC Default = 0x44, on VCC POR, VTR POR and HARD RESET Chip Level Vendor Defined Configuration ...

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REGISTER TEST 7 Default = 0x00 (when pin 117 is NC) 0x01(when pin 117 is connected to VTR) on VCC POR, VTR POR and HARD RESET TEST 6 Default = 0x00, on VCC POR and VTR POR TEST 4 Default ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet REGISTER TEST 3 Default = 0x00, on VCC POR and VTR POR Note 1: To allow the selection of the configuration address to a user defined location, these Configuration Address Bytes are ...

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LOGICAL DEVICE REGISTER I/O Base Address (see Device Base I/O Address Table) Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET Interrupt Select Defaults : 0x70 = 0x00 or 0x06 (Note) on VCC POR, VTR POR, ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet Table 11.5 - Primary Interrupt Select Configuration Register Description NAME REG INDEX Primary Interrupt 0x70 (R/W) Select Default=0x00 or 0x06 (Note 1) on VCC POR, VTR POR, HARD RESET and SOFT RESET ...

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For the PP logical device in ECP mode by setting dmaEn, bit D3 of the ecr. The DMA channel must be disabled if not used/selected by any Logical Device. Refer to Note A. Note 1: The default value of ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet 11.4 Logical Device I/O Address Table 11.7 and Table 11.8 summarize the logical device I/O addresses when LD_NUM bit is 0 and 1. Table 11.7 - Logical Device I/O Address, LD_NUM Bit ...

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LOGICAL DEVICE LOGICAL REGISTER NUMBER DEVICE INDEX Config. Config. Port 0x26, 0x27 Port Note 1 : This chip uses address bits [A11:A0] to decode the base address of each of its logical devices. Bit 6 of the OSC Global Configuration ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet LOGICAL DEVICE LOGICAL REGISTER INDEX NUMBER DEVICE 0x04 Serial Port 1 0x60,0x61 0x05 Reserved n/a 0x06 Reserved n/a 0x07 KYBD n/a 0x08 Reserved n/a 0x09 Reserved n/a 0x0A Runtime 0x60,0x61 Register Block ...

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Logical Device Configuration Registers The Logical Device Configuration Registers reset to their default values only on hard resets generated by VCC or VTR POR (as shown) or the nPCI_RESET signal. These registers are not affected by soft resets. Table ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME REG INDEX FDD Type Register Default = 0xFF on VCC POR, VTR POR and HARD RESET FDD0 Default = 0x00 on VCC POR, VTR POR and HARD RESET TEST9 Default = ...

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NAME REG INDEX IR Option Register Default = 0x02 on VCC POR, VTR POR and HARD RESET IR Half Duplex Timeout Default = 0x03 on VCC POR, VTR POR and HARD RESET Table 11.11 - Parallel Port Logical Device Configuration ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME REG INDEX PP Mode Register 2 Default = 0x00 on VCC POR, VTR POR and HARD RESET TEST10 Default = 0x08 on VCC POR, VTR POR and HARD RESET Table 11.12 ...

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Table 11.13 - Keyboard Logical Device Configuration Registers NAME REG INDEX KRST_GA20 Default = 0x00 on VCC POR, VTR POR and HARD RESET Bits[7:5] reset on VTR POR only Table 11.14 - Power Control/Runtime Register Block Logical Device Configuration Registers ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet NAME REG INDEX INT_G Default = 0x00 on VCC POR, VTR POR, HARD RESET and SOFT RESET SMSC/Non-SMSC Register Sets (Rev. 01-11-07) DEFINITION 0xF1 Bit[7:1] Reserved R/W Bit[0] INT_G Enable 0 = ...

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Chapter 12 Electrical Characteristics 12.1 Maximum Guaranteed Ratings Maximum 3.3 Supply ............................................................................................................................ +4.1V Maximum 5V Supply ............................................................................................................................. +6.0V Voltage on any 3.3V pin, with respect to Ground ......................................................................... -0.5 to 5.5V Voltage on any 5V pin, with respect to Ground ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER SYMBOL IS_400 Input Buffer Low Input Level High Input Level Schmitt Trigger Hystersis V ISPU_400 Input Buffer Low Input Level High Input Level Schmitt Trigger Hystersis V Pull-Up Input Low Current ...

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PARAMETER SYMBOL O12 Output Buffer Low Output Level High Output Level V OD12 Output Buffer Low Output Level High Output Level V OP14 Output Buffer Low Output Level High Output Level V OD24 Output Buffer Low Output Level High Output ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER SYMBOL ISOD8 Input/Output Buffer Low Input Level High Input Level Schmitt Trigger Hystersis V Low Output Level High Output Level V IPDO8 Input Buffer Low Input Level High Input Level Pull-Down ...

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PARAMETER SYMBOL IOD24 Input/Output Buffer Low Input Level High Input Level Low Output Level High Output Level V PCI Type Buffers 3.3V PCI 2.1 Compatible. (PCI_ICLK, PCI_I, PCI_O, PCI_IO) Leakage Current (ALL except IS, IS_400, ISPU_400, ISOD8, AO, O8_3V and ...

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Advanced I/O Controller with Motherboard GLUE Logic Datasheet PARAMETER SYMBOL 5V Tolerant Pins (All except PCI Buffers and nRSMRST) Input High Leakage Current ILEAK Input Low Leakage Current ILEAK 3.3V Main Supply Voltage VCC 3.3V Main Supply Current I 3.3V ...

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