LPC47N217N-ABZJ SMSC [SMSC Corporation], LPC47N217N-ABZJ Datasheet

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... Send/Receive 16-Byte FIFO — Supports 230k and 460k Baud — Programmable Baud Rate Generator — Modem Control Circuitry — Multiple Base I/O Address options and 15 IRQ Options SMSC LPC47N217N 56QFN LPC47N217N 56-Pin Super I/O with LPC Interface Multi-Mode Parallel Port with ChiProtect™ ...

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... LPC47N217N-ABZJ for 56-pin QFN Lead-free ROHS Compliant package LPC47N217N-ABZJ-TR for 56-pin QFN Lead-free ROHS Compliant package (tape and reel) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2009 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given ...

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... Super I/O with LPC Interface General Description The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 13 GPIO pins ...

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... CLKRUN# CLOCK GEN CLOCKI V Vcc GND TR Revision 0.3 (09-16-09) IO_PME# CONTROL, ADDRESS, DATA ACPI CONFIGURATION BLOCK REGISTERS Figure 1 LPC47N217N Block Diagram 4 PRODUCT PREVIEW 56-Pin Super I/O with LPC Interface PD[0:7], MULTI-MODE BUSY, SLCT, PARALLEL PE, nERROR, nACK PORT nSLCTIN, nALF nINIT, nSTROBE GP10, GP11, GP12*, GP13*, ...

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... TERMINAL #1 IDENTIFIER AREA (D1/2 X E1/ 45°X0.6 MAX (OPTIONAL) TOP VIEW SIDE VIEW 3-D VIEWS Figure 2 LPC47N217N 56-Pin QFN Package, 8x8mm Body, 0.5mm Pitch SMSC LPC47N217N 56QFN D2 e TERMINAL #1 3 IDENTIFIER AREA (D/2 X E/2) E2 EXPOSED PAD 2 56X L 2 56X b BOTTOM VIEW NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETER. 2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± ...