MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 105

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68H(R)C908JL3
MOTOROLA
—
Rev. 1.0
If V
entry
the external clock input to OSC1. If PTB3 is high with V
to IRQ1 upon monitor mode entry
frequency is a divide-by-four of the external clock input to OSC1. Holding
the PTB3 pin low when entering monitor mode causes a bypass of a
divide-by-two stage at the oscillator only if V
In this event, the OSCOUT frequency is equal to the 2OSCOUT
frequency, and OSC1 input directly generates internal bus clocks. In this
case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Entering monitor mode with V
long as V
7. System Integration Module (SIM)
operation.)
If entering monitor mode without high voltage on IRQ1 and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ1 or the RST.
Figure
the reset vector is blank and IRQ1 = V
(XTALCLK or RCCCLK) of 9.8304MHz is required for a baud rate of
9600.
DD
(Table 9-1
+V
9-2. shows a simplified diagram of the monitor mode entry when
DD
HI
is applied to IRQ1 and PTB3 is low upon monitor mode
+ V
Monitor ROM (MON)
HI
condition set 1), the bus frequency is a divide-by-two of
is applied to either the IRQ1 or the RST. (See
DD
), then all port B pin requirements and conditions,
DD
+ V
(Table 9-1
(Table 9-1
HI
for more information on modes of
DD
on IRQ1, the COP is disabled as
. An oscillator frequency
DD
condition set 3, where
condition set 2), the bus
+V
HI
is applied to IRQ1.
Functional Description
Monitor ROM (MON)
DD
+V
Technical Data
HI
Section
applied
105