MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 107

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

9.4.2 Baud Rate
MC68H(R)C908JL3
MOTOROLA
—
Rev. 1.0
Table 9-2
and monitor mode.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
The communication baud rate is dependant on oscillator frequency. The
state of PTB3 also affects baud rate if entry to monitor mode is by
IRQ1 = V
PTB3 pin is at logic zero upon entry into monitor mode, the divide by ratio
is 512.
Monitor
Modes
User
Notes:
1. If the high voltage (V
Blank reset vector,
IRQ1 = V
Monitor Mode
asserts its COP enable output. The COP is a mask option enabled or disabled by the
COPD bit in the configuration register.
IRQ1 = V
Entry By:
DD
Disabled
is a summary of the vector differences between user mode
DD
Enabled
+ V
Table 9-2. Monitor Mode Vector Differences
COP
DD
+ V
Table 9-3. Monitor Baud Rate Selection
Monitor ROM (MON)
HI
HI
(1)
. When PTB3 is high, the divide by ratio is 1024. If the
DD
Vector
$FEFE
$FFFE
Reset
High
+ V
Input Clock
4.9152 MHz
9.8304 MHz
4.9152 MHz
9.8304 MHz
4.9152 MHz
Frequency
HI
) is removed from the IRQ1 pin or the RST pin, the SIM
Vector
$FEFF
$FFFF
Reset
Low
Functions
$FEFC
Vector
$FFFC
Break
High
PTB3
X
X
0
1
1
$FEFD
Vector
$FFFD
Break
Low
Functional Description
Monitor ROM (MON)
Baud Rate
$FEFC
9600 bps
9600 bps
4800 bps
9600 bps
4800 bps
Vector
$FFFC
High
SWI
Technical Data
$FEFD
Vector
$FFFD
Low
SWI
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