MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 156

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

I/O Ports
12.6.2 Data Direction Register D (DDRD)
Technical Data
156
NOTE:
Address:
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
the port D I/O logic.
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
READ DDRD ($0007)
WRITE DDRD ($0007)
WRITE PTD ($0003)
READ PTD ($0003)
$0007
Bit 7
Figure 12-10. Data Direction Register D (DDRD)
0
DDRD6
6
0
Figure 12-11. Port D I/O Circuit
I/O Ports
RESET
DDRD5
5
0
DDRD4
DDRDx
PTDx
4
0
DDRD3
3
0
MC68H(R)C908JL3
PTD[0:3] To Analog-To-Digital Converter
PTD[4:5] To Timer
DDRD2
Figure 12-11
2
0
PTDPU[6:7]
DDRD1
1
0
MOTOROLA
—
shows
5k
Rev. 1.0
DDRD0
Bit 0
0
PTDx