MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 69

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

INH Inherent
IMM Immediate
DIR Direct
EXT Extended
DD
IX+D Indexed-Direct
*
LSB
Pre-byte for stack pointer indexed instructions
A
B
C
D
E
0
1
2
3
4
5
6
7
8
9
F
MSB
Direct-Direct
BRSET0
3
BRCLR0
3
BRSET1
3
BRCLR1
3
BRSET2
3
BRCLR2
3
BRSET3
3
BRCLR3
3
BRSET4
3
BRCLR4
3
BRSET5
3
BRCLR5
3
BRSET6
3
BRCLR6
3
BRSET7
3
BRCLR7
3
Bit Manipulation
DIR
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
REL Relative
IX
IX1
IX2
IMD Immediate-Direct
DIX+ Direct-Indexed
DIR
1
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Indexed, No Offset
Indexed, 8-Bit Offset
Indexed, 16-Bit Offset
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Branch
BHCC
BHCS
BRA
BRN
BCC
BCS
BNE
BEQ
BMC
BMS
REL
BLS
BPL
BHI
BMI
BIH
BIL
2
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
REL
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
3
2
2
2
2
2
2
2
2
3
2
2
2
CBEQ
STHX
DBNZ
COM
NEG
ROR
DEC
LSR
ASR
ROL
TST
CLR
DIR
LSL
INC
3
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
4
5
4
4
4
4
4
4
4
4
5
4
3
3
1
3
1
1
1
3
1
1
1
1
1
2
1
1
3
1
CBEQA
DBNZA
NEGA
COMA
RORA
LSRA
LDHX
ASRA
ROLA
DECA
CLRA
LSLA
INCA
TSTA
MOV
MUL
SP1 Stack Pointer, 8-Bit Offset
SP2 Stack Pointer, 16-Bit Offset
IX+ Indexed, No Offset with
IX1+ Indexed, 1-Byte Offset with
INH
4
INH
IMM
INH
INH
INH
IMM
INH
INH
INH
INH
INH
INH
INH
INH
DD
INH
1
4
5
1
1
3
1
1
1
1
1
3
1
1
5
1
Post Increment
Post Increment
Read-Modify-Write
1
3
1
1
1
2
1
1
1
1
1
2
1
1
2 DIX+
1
CBEQX
DBNZX
NEGX
COMX
RORX
LSRX
LDHX
ASRX
ROLX
DECX
CLRX
LSLX
TSTX
INCX
MOV
INH
DIV
5
INH
IMM
INH
INH
INH
DIR
INH
INH
INH
INH
INH
INH
INH
INH
INH
1
4
7
1
1
4
1
1
1
1
1
3
1
1
4
1
2
3 IX1+
1
2
2
3
2
2
2
2
2
3
2
2
3
2
CBEQ
CPHX
DBNZ
COM
MOV
NEG
NSA
ROR
ASR
ROL
DEC
CLR
LSR
LSL
TST
INC
IX1
6
INH
IX1
IX1
IMM
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IMD
IX1
4
5
3
4
4
3
4
4
4
4
4
5
4
3
4
3
IX1
Table 6-2. Opcode Map
3
4
3
3
3
3
3
3
3
4
3
3
3
CBEQ
DBNZ
COM
NEG
ROR
ASR
ROL
DEC
SP1
LSR
TST
CLR
9E6
LSL
INC
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
5
6
5
5
5
5
5
5
6
5
4
4
5
1
2
1
1
1
2
1
1
1
1
1
2
1
1
2 IX+D
1
CBEQ
CPHX
DBNZ
COM
NEG
ROR
DEC
MOV
DAA
LSR
ASR
ROL
TST
CLR
LSL
INC
Low Byte of Opcode in Hexadecimal
IX
7
IX
IX+
INH
IX
IX
DIR
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
4
2
3
3
4
3
3
3
3
3
4
3
2
4
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
PSHH
PULA
PSHA
PULX
PSHX
PULH
CLRH
STOP
WAIT
RTS
SWI
TAP
TPA
INH
RTI
8
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
7
4
9
2
1
2
2
2
2
2
2
1
1
1
Control
2
2
2
2
1
1
1
1
1
1
1
1
1
1
NOP
BGE
BGT
TXS
TSX
CLC
SEC
RSP
TXA
BLT
BLE
TAX
INH
CLI
SEI
9
*
REL
REL
REL
REL
INH
INH
INH
INH
INH
INH
INH
INH
INH
INH
3
3
3
3
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
BSR
IMM
LDA
LDX
BIT
AIS
AIX
A
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
IMM
REL
IMM
IMM
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
LSB
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
STA
JMP
JSR
LDX
STX
DIR
BIT
B
0
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
DIR
MSB
3
3
3
3
3
3
3
3
3
3
3
3
2
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BRSET0
3
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
EXT
LDA
STA
JMP
JSR
LDX
STX
BIT
C
0
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
EXT
DIR
4
4
4
4
4
4
4
4
4
4
4
4
3
5
4
4
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
High Byte of Opcode in Hexadecimal
Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode
Register/Memory
CMP
AND
EOR
ADC
ORA
ADD
SUB
SBC
CPX
LDA
JMP
JSR
LDX
STX
STA
BIT
IX2
D
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
IX2
4
4
4
4
4
4
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
CMP
EOR
ORA
9ED
SUB
SBC
CPX
AND
LDA
ADC
ADD
LDX
STX
SP2
STA
BIT
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
SP2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
CMP
EOR
ORA
SUB
SBC
CPX
AND
ADC
ADD
JMP
LDX
STX
LDA
STA
JSR
BIT
IX1
E
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
IX1
3
3
3
3
3
3
3
3
3
3
3
3
3
5
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
CMP
SUB
SBC
CPX
AND
EOR
ADC
ORA
ADD
SP1
9EE
LDA
STA
LDX
STX
BIT
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
SP1
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SUB
CMP
SBC
CPX
AND
EOR
ADC
ORA
ADD
LDA
STA
JMP
JSR
LDX
STX
BIT
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
2
2
2
2
2
2
2
2
2
2
2
2
2
4
2
2