MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 75

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

7.3 SIM Bus Clock Control and Generation
7.3.1 Bus Timing
7.3.2 Clock Start-Up from POR
7.3.3 Clocks in Stop Mode and Wait Mode
MC68H(R)C908JL3
MOTOROLA
—
Rev. 1.0
The bus clock generator provides system clock signals for the CPU and
peripherals on the MCU. The system clocks are generated from an
incoming clock, OSCOUT, as shown in
In user mode, the internal bus frequency is the oscillator frequency
(2OSCOUT) divided by four.
When the power-on reset module generates a reset, the clocks to the
CPU and peripherals are inactive and held in an inactive phase until after
the 4096 2OSCOUT cycle POR time-out has completed. The RST pin is
driven low by the SIM during this entire period. The IBUS clocks start
upon completion of the time-out.
Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
2OSCOUT to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay time-out. This time-out is
selectable as 4096 or 32 2OSCOUT cycles. (See
OSCILLATOR
OSCILLATOR
System Integration Module (SIM)
From
From
Figure 7-3. SIM Clock Signals
2OSCOUT
OSCOUT
SIM COUNTER
2
SIM
SIM Bus Clock Control and Generation
Figure
GENERATORS
BUS CLOCK
System Integration Module (SIM)
7-3.
7.7.2 Stop
Technical Data
Mode.)
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