MC68HC908JK3 MOTOROLA [Motorola, Inc], MC68HC908JK3 Datasheet - Page 76

• Manufacturer Part Number: MC68HC908JK3
• Description: MC68HC908JK1
• Manufacturer: MOTOROLA [Motorola, Inc]

System Integration Module (SIM)
7.4 Reset and System Initialization
7.4.1 External Pin Reset
Technical Data
76
In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.
The MCU has these reset sources:
All of these resets produce the vector $FFFE–FFFF ($FEFE–FEFF in
Monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.
An internal reset clears the SIM counter (see
external reset does not. Each of the resets sets a corresponding bit in
the reset status register (RSR). (See
The RST pin circuits include an internal pull-up device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the reset
status register (RSR) is set as long as RST is held low for a minimum of
67 2OSCCLK cycles, assuming that the POR was not the source of the
reset. See
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Reset Type
Power-on reset module (POR)
External reset pin (RST)
Computer operating properly module (COP)
Low-voltage inhibit module (LVI)
Illegal opcode
Illegal address
All others
POR
System Integration Module (SIM)
Table 7-2
Table 7-2. PIN Bit Set Timing
for details.
Number of Cycles Required to Set PIN
Figure 7-4
4163 (4096 + 64 + 3)
7.8 SIM
67 (64 + 3)
shows the relative timing.
7.5 SIM
MC68H(R)C908JL3
Registers.)
Counter), but an
MOTOROLA
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Rev. 1.0