MC68HC908JK3EMP MOTOROLA [Motorola, Inc], MC68HC908JK3EMP Datasheet
MC68HC908JK3EMP
Related parts for MC68HC908JK3EMP
MC68HC908JK3EMP Summary of contents
Page 1
M68HC08 Microcontrollers MOTOROLA.COM/SEMICONDUCTORS MC68HC908JL3E MC68HC908JK3E MC68HC908JK1E MC68HRC908JL3E MC68HRC908JK3E MC68HRC908JK1E MC68HLC908JL3E MC68HLC908JK3E MC68HLC908JK1E Technical Data MC68HC908JL3E/D Rev. 2, 12/2002 ...
Page 2
...
Page 3
MC68HC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume ...
Page 4
Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer ...
Page 5
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 1. General Description . . . . . . . . . . . . . . . . . . . . 23 Section 2. Memory Map . . . . . . . ...
Page 6
List of Sections Technical Data 6 MC68H(R)C908JL3E/JK3E/JK1E List of Sections Rev. 2.0 — MOTOROLA ...
Page 7
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 1.1 1.2 1.3 1.4 1.5 1.6 2.1 2.2 2.3 2.4 3.1 3.2 3.3 4.1 4.2 4.3 MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Section 1. General Description Contents . . . . . . . . . . . . . ...
Page 8
Table of Contents 4.4 4.5 4.6 4.7 4.8 4.9 5.1 5.2 5.3 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 6.6.1 6.6.2 6.7 6.8 6.9 Technical Data 8 FLASH Control Register . . . . . . ...
Page 9
MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Section 7. System Integration Module ...
Page 10
Table of Contents 7.8.1 7.8.2 7.8.3 8.1 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.6 8.6.1 8.6.2 8.7 9.1 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 Technical Data 10 Break Status Register (BSR ...
Page 11
I/O Registers ...
Page 12
Table of Contents 11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 11.6.1 11.6.2 11.7 11.7.1 11.8 11.8.1 11.8.2 11.8.3 12.1 12.2 12.3 12.3.1 12.3.2 12.3.3 12.4 12.4.1 12.4.2 Technical Data 12 Section 11. Analog-to-Digital Converter (ADC) Contents ...
Page 13
MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Port ...
Page 14
Table of Contents 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 15.5 15.6 15.7 15.8 15.8.1 15.8.2 15.9 16.1 16.2 16.3 16.4 16.5 16.6 16.6.1 16.6.2 17.1 17.2 17.3 Technical Data 14 I/O Signals . . . . . . ...
Page 15
Control Timing . . . . . . . . . . . . . . ...
Page 16
Table of Contents 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20.1 20.2 20.3 A.1 A.2 A.3 A.4 A.5 A.6 A.6.1 A.6.2 A.6.3 A.6.4 A.6.5 A.6.6 A.7 Technical Data 16 Section 19. Mechanical Specifications Contents . . . . . . ...
Page 17
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Figure 1-1 1-2 1-3 1-4 2-1 2-2 4-1 4-2 4-3 4-4 5-1 5-2 6-1 6-2 6-3 6-4 6-5 6-6 7-1 7-2 7-3 7-4 7-5 7-6 7-7 MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA MCU Block Diagram . . . . . ...
Page 18
List of Figures Figure 7-8 7-9 7-10 Interrupt Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 19
Figure 11-1 ADC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . .144 11-2 ADC Block Diagram . . . . ...
Page 20
List of Figures Figure 17-1 Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 191 17-2 Break I/O Register Summary ...
Page 21
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Table 1-1 1-2 2-1 6-1 6-2 7-1 7-2 7-3 7-4 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 10-1 Pin Name Conventions . . . . . . . . . . . . . ...
Page 22
List of Tables Table 12-1 Port Control Register Bits Summary 155 12-2 Port A Pin Functions . . . . . ...
Page 23
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 1.1 Contents 1.2 1.3 1.4 1.5 1.6 1.2 Introduction The MC68H(R)C908JL3E is a member of the low-cost, high- performance M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 Family is based on the customer-specified integrated circuit ...
Page 24
General Description All references to the MC68H(R)C908JL3E in this data book apply equally to the MC68H(R)C908JK3E and MC68H(R)C908JK1E, unless otherwise stated. 1.3 Features Features of the MC68H(R)C908JL3E include the following: • EMC enhanced version of MC68H(R)C908JL3/JK3/JK1 • High-performance M68HC08 architecture ...
Page 25
Features of the CPU08 include the following: • • • • • • • • • • MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA 15 general purpose I/O ports for MC68H(R)C908JK3E/JK1E: – 1 keyboard interrupt with internal pull-up (MC68HRC908JK3E/JK1E ...
Page 26
General Description 1.4 MCU Block Diagram Figure 1-1 M68HC08 CPU CPU ARITHMETIC/LOGIC REGISTERS UNIT (ALU) CONTROL AND STATUS REGISTERS — 64 BYTES USER FLASH: MC68H(R)C908JK3E/JL3E — 4,096 BYTES MC68H(R)C908JK1E — 1,536 BYTES USER RAM — 128 BYTES MONITOR ROM — ...
Page 27
Pin Assignments OSC2/RCCLK/PTA6/KBI OSC2/RCCLK/PTA6/KBI MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA 28 IRQ1 1 PTA0/KBI0 27 2 VSS 3 26 OSC1 PTA1/KBI1 6 23 VDD 22 7 PTA2/KBI2 8 21 PTA3/KBI3 9 20 PTB7/ADC7 19 10 PTB6/ADC6 11 18 PTB5/ADC5 ...
Page 28
General Description OSC1 OSC2/RCCLK/PTA6/KBI6 PTA1/KBI1 NC VDD PTA2/KBI2 PTA3KBI3 PTB7/ADC7 NC: No connection Figure 1-4. 48-Pin LQFP Pin Assignment Technical Data MC68H(R)C908JL3E MC68H(R)C908JL3E/JK3E/JK1E ...
Page 29
Pin Functions Description of the pin functions are provided in PIN NAME VDD Power supply. VSS Power supply ground RESET input, active low. RST With Internal pull-up and schmitt trigger input. External IRQ pin. With software programmable internal pull-up ...
Page 30
General Description Technical Data 30 MC68H(R)C908JL3E/JK3E/JK1E General Description Rev. 2.0 — MOTOROLA ...
Page 31
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 2.1 Contents 2.2 2.3 2.4 2.2 Introduction The CPU08 can address 64 Kbytes of memory space. The memory map, shown in MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Introduction . . . . . . . . . . . . ...
Page 32
Memory Map $0000 I/O REGISTERS ↓ 64 BYTES $003F $0040 RESERVED ↓ 64 BYTES $007F $0080 ↓ 128 BYTES $00FF $0100 UNIMPLEMENTED ↓ 60,160 BYTES $EBFF $EC00 FLASH MEMORY ↓ MC68H(R)C908JL3E/JK3E $FBFF 4,096 BYTES $FC00 MONITOR ROM ↓ 512 BYTES ...
Page 33
I/O Section Addresses $0000–$003F, shown in control, status, and data registers. Additional I/O registers have the following addresses: • • • • • • • • • • • • • • • • • 2.4 Monitor ROM The ...
Page 34
Memory Map Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: $0002 Unimplemented Write: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: Data Direction Register ...
Page 35
Addr. Register Name Read: $000B ↓ Unimplemented Write: $000C Read: Port A Input Pull-up $000D Enable Register Write: (PTAPUE) Reset: $000E Read: ↓ Write: Unimplemented $0019 Read: Keyboard Status and $001A Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt $001B ...
Page 36
Memory Map Addr. Register Name Read: TIM Counter Register $0021 High Write: (TCNTH) Reset: Read: TIM Counter Register $0022 Low Write: (TCNTL) Reset: Read: TIM Counter Modulo $0023 Register High Write: (TMODH) Reset: Read: TIM Counter Modulo $0024 Register Low ...
Page 37
Addr. Register Name $002B Read: ↓ Unimplemented Write: $003B Read: ADC Status and Control $003C Register Write: (ADSCR) Reset: Read: ADC Data Register $003D Write: (ADR) Reset: Read: ADC Input Clock Register $003E Write: (ADICLK) Reset: Read: $003F Unimplemented Write: ...
Page 38
Memory Map Addr. Register Name Read: Interrupt Status Register 2 $FE05 Write: (INT2) Reset: Read: Interrupt Status Register 3 $FE06 Write: (INT3) Reset: Read: $FE07 Reserved Write: Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: FLASH Block Protect $FE09 ...
Page 39
Vector Priority MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Table 2-1. Vector Addresses INT Flag Address $FFD0 Lowest ↓ — $FFDD $FFDE IF15 $FFDF $FFE0 IF14 $FFE1 IF13 ↓ — IF6 $FFF2 IF5 $FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 IF2 — $FFFA IF1 $FFFB ...
Page 40
Memory Map Technical Data 40 MC68H(R)C908JL3E/JK3E/JK1E Memory Map Rev. 2.0 — MOTOROLA ...
Page 41
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 3. Random-Access Memory (RAM) 3.1 Contents 3.2 3.3 3.2 Introduction This section describes the 128 bytes of RAM. 3.3 Functional Description Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is ...
Page 42
Random-Access Memory (RAM) During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may ...
Page 43
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 4.1 Contents 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.2 Introduction This section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. ...
Page 44
FLASH Memory (FLASH) Addr. Register Name Read: FLASH Control Register $FE08 Write: (FLCR) Reset: Read: FLASH Block Protect $FE09 Register Write: (FLBPR) Reset: Figure 4-1. FLASH I/O Register Summary 4.3 Functional Description The FLASH memory consists of an array of ...
Page 45
FLASH Control Register The FLASH Control Register controls FLASH program and erase operations. Address: Read: Write: Reset: HVEN — High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program ...
Page 46
FLASH Memory (FLASH) 4.5 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area ...
Page 47
FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH Control 2. Write any data to any FLASH location within the FLASH ...
Page 48
FLASH Memory (FLASH) 4.7 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step ...
Page 49
Algorithm for programming a row (32 bytes) of FLASH memory NOTE: The time between each FLASH address change (step 6 to step 6), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step ...
Page 50
FLASH Memory (FLASH) 4.8 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations ...
Page 51
The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start ...
Page 52
FLASH Memory (FLASH) Technical Data 52 MC68H(R)C908JL3E/JK3E/JK1E FLASH Memory (FLASH) Rev. 2.0 — MOTOROLA ...
Page 53
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 5. Configuration Register (CONFIG) 5.1 Contents 5.2 5.3 5.2 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Introduction . . . . ...
Page 54
Configuration Register (CONFIG) 5.3 Functional Description The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various ...
Page 55
Address: Read: Write: Reset: COPRS — COP reset period selection bit LVID — Low Voltage Inhibit Disable Bit SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles ...
Page 56
Configuration Register (CONFIG) Technical Data 56 MC68H(R)C908JL3E/JK3E/JK1E Configuration Register (CONFIG) Rev. 2.0 — MOTOROLA ...
Page 57
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 6.1 Contents 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 6.6.1 6.6.2 6.7 6.8 6.9 6.2 Introduction The M68HC08 CPU (central processor unit enhanced and fully object-code-compatible version of the M68HC05 CPU. ...
Page 58
Central Processor Unit (CPU) 6.3 Features • Object code fully upward-compatible with M68HC05 Family • 16-bit stack pointer with stack manipulation instructions • 16-bit index register with x-register manipulation instructions • 8-MHz CPU internal bus frequency • 64-Kbyte program/data memory ...
Page 59
Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Read: Write: Reset: MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA ...
Page 60
Central Processor Unit (CPU) 6.4.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index ...
Page 61
Read: Write: Reset: NOTE: The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer ...
Page 62
Central Processor Unit (CPU) 6.4.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to logic 1. The ...
Page 63
NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After ...
Page 64
Central Processor Unit (CPU) 6.5 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing ...
Page 65
CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: • • The break interrupt begins after completion of the CPU instruction in progress. If the break address register ...
Page 66
Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form ADC #opr ADC opr ADC opr ADC opr,X Add with Carry ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X Add ...
Page 67
Source Operation Form BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal Branch if Greater Than or Equal To BGE opr (Signed Operands) Branch if Greater Than (Signed BGT opr Operands) BHCC rel Branch ...
Page 68
Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form BRCLR n,opr,rel Branch if Bit Clear BRN rel Branch Never BRSET n,opr,rel Branch if Bit Set BSET n,opr Set Bit n in ...
Page 69
Source Operation Form CMP #opr CMP opr CMP opr CMP opr,X Compare A with M CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX Complement (One’s Complement) COM opr,X COM ,X COM opr,SP CPHX #opr Compare H:X ...
Page 70
Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form EOR #opr EOR opr EOR opr EOR opr,X Exclusive OR M with A EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX Increment INC opr,X ...
Page 71
Source Operation Form LSR opr LSRA LSRX Logical Shift Right LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ Move MOV #opr,opr MOV X+,opr MUL Unsigned multiply NEG opr NEGA NEGX Negate (Two’s Complement) NEG opr,X NEG ,X NEG ...
Page 72
Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form ROR opr RORA RORX Rotate Right through Carry ROR opr,X ROR ,X ROR opr,SP RSP Reset Stack Pointer RTI Return from Interrupt RTS Return from Subroutine SBC #opr ...
Page 73
Source Operation Form SUB #opr SUB opr SUB opr SUB opr,X Subtract SUB opr,X SUB ,X SUB opr,SP SUB opr,SP SWI Software Interrupt TAP Transfer A to CCR TAX Transfer TPA Transfer CCR to A TST opr ...
Page 74
Central Processor Unit (CPU) Table 6-1. Instruction Set Summary Source Operation Form A Accumulator C Carry/borrow bit CCR Condition code register dd Direct address of operand dd rr Direct address of operand and relative offset of branch instruction DD Direct ...
Page 75
Bit Manipulation Branch Read-Modify-Write DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR 1 INH ...
Page 76
Central Processor Unit (CPU) Technical Data 76 MC68H(R)C908JL3E/JK3E/JK1E Central Processor Unit (CPU) Rev. 2.0 — MOTOROLA ...
Page 77
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 7. System Integration Module (SIM) 7.1 Contents 7.2 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 7.4.2.1 7.4.2.2 7.4.2.3 7.4.2.4 7.4.2.5 7.5 7.5.1 7.5.2 7.5.3 7.6 7.6.1 7.6.1.1 7.6.1.2 7.6.2 7.6.2.1 7.6.2.2 7.6.2.3 7.6.3 7.6.4 7.6.5 ...
Page 78
System Integration Module (SIM) 7.7 7.7.1 7.7.2 7.8 7.8.1 7.8.2 7.8.3 7.2 Introduction This section describes the system integration module (SIM), which supports external and/or internal interrupts. Together with the CPU, the SIM controls all MCU activities. ...
Page 79
VDD INTERNAL PULL-UP RESET PIN LOGIC SIM RESET STATUS REGISTER Signal Name 2OSCOUT Buffered clock from the X-tal oscillator circuit or the RC oscillator circuit. The 2OSCOUT frequency divided by two. This signal is again divided by two in the ...
Page 80
System Integration Module (SIM) Addr. Register Name Read: Break Status Register $FE00 Write: (BSR) Reset: Note: Writing a logic 0 clears SBSW. Read: Reset Status Register $FE01 Write: (RSR) POR: Read: $FE02 Reserved Write: Reset: Read: Break Flag Control $FE03 ...
Page 81
SIM Bus Clock Control and Generation The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, OSCOUT, as shown in 7.3.1 Bus Timing In ...
Page 82
System Integration Module (SIM) 7.4 Reset and System Initialization The MCU has these reset sources: • Power-on reset module (POR) • External reset pin (RST) • Computer operating properly module (COP) • Low-voltage inhibit module (LVI) • Illegal opcode • ...
Page 83
Active Resets from Internal Sources All internal reset sources actively pull the RST pin low for 32 2OSCOUT cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles ...
Page 84
System Integration Module (SIM) 7.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power-on has occurred. The external reset pin (RST) is held low while the SIM ...
Page 85
Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the reset status register (RSR). The ...
Page 86
System Integration Module (SIM) 7.4.2.5 LVI Reset The low-voltage inhibit module (LVI) asserts its output to the SIM when the V DD reset status register (SRSR) is set, and the external reset pin (RSTB) is held low while the SIM ...
Page 87
SIM Counter and Reset States External reset has no effect on the SIM counter. (See for details.) The SIM counter is free-running after all reset states. (See 7.4.2 Active Resets from Internal Sources internal reset recovery sequences.) 7.6 Exception ...
Page 88
System Integration Module (SIM) BREAK INTERRUPT? YES (As many interrupts as exist on chip) Technical Data 88 FROM RESET YES I BIT SET BIT SET? NO YES IRQ INTERRUPT? NO TIMER YES INTERRUPT? NO STACK CPU REGISTERS. LOAD ...
Page 89
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register ...
Page 90
System Integration Module (SIM) If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. demonstrates what happens when two interrupts are pending interrupt is pending upon exit ...
Page 91
SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software ...
Page 92
System Integration Module (SIM) 7.6.2.1 Interrupt Status Register 1 Address: Read: Write: Reset: IF1, IF3 to IF5 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown Interrupt request present 0 = ...
Page 93
Interrupt Status Register 3 Address: Read: Write: Reset: IF15 — Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Bit — Always read 0 7.6.3 Reset All reset sources always ...
Page 94
System Integration Module (SIM) 7.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly ...
Page 95
Wait mode can also be exited by a reset or break. A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the mask option ...
Page 96
System Integration Module (SIM) 7.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the ...
Page 97
INT/BREAK IAB Figure 7-19. Stop Mode Recovery from Interrupt or Break 7.8 SIM Registers The SIM has three memory mapped registers. mapping of these registers. 7.8.1 Break Status Register (BSR) The break status register contains a flag to indicate ...
Page 98
System Integration Module (SIM) SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset ...
Page 99
Address: Read: Write: POR: POR — Power-On Reset Bit PIN — External Reset Bit COP — Computer Operating Properly Reset Bit ILOP — Illegal Opcode Reset Bit ILAD — Illegal Address Reset Bit (opcode fetches only) MODRST — Monitor Mode ...
Page 100
System Integration Module (SIM) 7.8.3 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU break state. Address: $FE03 Bit 7 Read: BCFE Write: Reset: ...
Page 101
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 8.1 Contents 8.2 8.3 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.6 8.6.1 8.6.2 8.7 8.2 Introduction The oscillator module provides the reference clock for the MCU system and bus. Two types of oscillator ...
Page 102
Oscillator (OSC) 8.3 X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E) The X-tal oscillator circuit is designed for use with an external crystal or ceramic resonator to provide accurate clock source. In its typical configuration, the X-tal oscillator is connected in a Pierce oscillator configuration, ...
Page 103
The series resistor (R oscillator guidelines and may not be required for all ranges of operation, especially with high frequency crystals. Refer to the crystal manufacturer’s data for more information. 8.4 RC Oscillator (MC68HRC908JL3E/JK3E/JK1E) The RC oscillator circuit is designed ...
Page 104
Oscillator (OSC) 8.5 I/O Signals The following paragraphs describe the oscillator I/O signals. 8.5.1 Crystal Amplifier Input Pin (OSC1) OSC1 pin is an input to the crystal oscillator amplifier or the input to the RC oscillator circuit. 8.5.2 Crystal Amplifier ...
Page 105
RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of the external R and C. shows only the logical relation of RCCLK to OSC1 and may not represent ...
Page 106
Oscillator (OSC) 8.7 Oscillator During Break Mode The oscillator continues to drive OSCOUT and 2OSCOUT when the device enters the break state. Technical Data 106 MC68H(R)C908JL3E/JK3E/JK1E Oscillator (OSC) Rev. 2.0 — MOTOROLA ...
Page 107
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 9.1 Contents 9.2 9.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 9.2 Introduction This section describes the monitor ROM (MON) and the monitor mode entry methods. The monitor ROM allows complete testing of the MCU ...
Page 108
Monitor ROM (MON) 9.3 Features Features of the monitor ROM include the following: • Normal user-mode pin functionality • One pin dedicated to serial communication between monitor ROM and host computer • Standard mark/space non-return-to-zero (NRZ) communication with host computer ...
Page 109
FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION B FOR MC68HC908JL3E/JK3E/JK1E SW1 AT POSITION FOR MC68HRC908JL3E/JK3E/JK1E SW1 MUST BE AT POSITION A MAX232 C1 µ C1– GND 2 4 ...
Page 110
Monitor ROM (MON) 9.4.1 Entering Monitor Mode Table 9-1 specified in the table, monitor mode may be entered after a POR and will allow communication at 9600 baud provided one of the following sets of conditions is met ...
Page 111
If V (Table 9-1 clock input to OSC1. If PTB3 is high with V monitor mode entry divide-by-four of the clock input to OSC1. Holding the PTB3 pin low when entering monitor mode causes a bypass of a divide-by-two stage ...
Page 112
Monitor ROM (MON) Figure 9-2. Low-Voltage Monitor Mode Entry Flowchart Enter monitor mode with the pin configuration shown above by pulling RST low and then high. The rising edge of RST latches monitor mode. Once monitor mode is latched, the ...
Page 113
Table 9-2 and monitor mode. Modes User Monitor Notes the high voltage (V When the host computer has completed downloading code into the MCU RAM, the host then sends a RUN command, which executes an RTI, which sends ...
Page 114
Monitor ROM (MON) 9.4.3 Data Format Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. (See START BIT $A5 BREAK The data transmit and receive rate can be anywhere from 4800 baud to 28.8k-baud. Transmit and ...
Page 115
Break Signal A start bit followed by nine low bits is a break signal. (See When the monitor receives a break signal, it drives the PTB0 pin high for the duration of two bits before echoing the break signal. ...
Page 116
Monitor ROM (MON) Table 9-4. READ (Read Memory) Command Description Read byte from memory Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of specified address Opcode $4A Command Sequence SENT TO MONITOR READ READ ECHO ...
Page 117
Table 9-6. IREAD (Indexed Read) Command Description Read next 2 bytes in memory from last address accessed Operand Specifies 2-byte address in high byte:low byte order Data Returned Returns contents of next two addresses Opcode $1A Command Sequence SENT TO ...
Page 118
Monitor ROM (MON) Table 9-8. READSP (Read Stack Pointer) Command Description Reads stack pointer Operand None Data Returned Returns stack pointer in high byte:low byte order Opcode $0C Command Sequence SENT TO MONITOR READSP READSP ECHO Table 9-9. RUN (Run ...
Page 119
Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6–$FFFD. Locations $FFF6–$FFFD ...
Page 120
Monitor ROM (MON) Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6–$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH ...
Page 121
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 10.1 Contents 10.2 10.3 10.4 10.5 10.5.1 10.5.2 10.5.3 10.5.3.1 10.5.3.2 10.5.4 10.5.4.1 10.5.4.2 10.5.4.3 10.6 10.7 10.7.1 10.7.2 10.8 10.9 10.10 I/O Registers ...
Page 122
Timer Interface Module (TIM) 10.2 Introduction This section describes the timer interface module (TIM2, Version B). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 10-1 10.3 Features Features ...
Page 123
Functional Description Figure 10-1 the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM ...
Page 124
Timer Interface Module (TIM) Addr. Register Name TIM Status and Control $0020 Register (TSC) TIM Counter Register High $0021 (TCNTH) TIM Counter Register Low $0022 (TCNTL) TIM Counter Modulo $0023 Register High (TMODH) TIM Counter Modulo $0024 Register Low (TMODL) ...
Page 125
TIM Channel 1 $0029 Register High (TCH1H) TIM Channel 1 $002A Register Low (TCH1L) 10.5.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs. The prescaler generates seven clock rates from the internal bus clock. ...
Page 126
Timer Interface Module (TIM) 10.5.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in unbuffered because changing the output compare value requires writing the new value over the old value currently in the ...
Page 127
Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B ...
Page 128
Timer Interface Module (TIM) TCHx The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) ...
Page 129
Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: • • NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable ...
Page 130
Timer Interface Module (TIM) NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active ...
Page 131
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSC0) controls and monitors the PWM signal from the ...
Page 132
Timer Interface Module (TIM) 10.7.1 Wait Mode The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring ...
Page 133
I/O Signals Port D shares two of its pins with the TIM. The two TIM channel I/O pins are PTD4/TCH0 and PTD5/TCH1. Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. ...
Page 134
Timer Interface Module (TIM) 10.10.1 TIM Status and Control Register (TSC) The TIM status and control register does the following: • Enables TIM overflow interrupts • Flags TIM overflows • Stops the TIM counter • Resets the TIM counter • ...
Page 135
TSTOP — TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. NOTE: Do not set the TSTOP bit ...
Page 136
Timer Interface Module (TIM) 10.10.2 TIM Counter Registers (TCNTH:TCNTL) The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte ...
Page 137
TIM Counter Modulo Registers (TMODH:TMODL) The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from ...
Page 138
Timer Interface Module (TIM) 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1) Each of the TIM channel status and control registers does the following: • Flags input captures and output compares • Enables input capture and output compare interrupts • ...
Page 139
CHxF — Channel x Flag Bit When channel input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel output compare channel, CHxF is set ...
Page 140
Timer Interface Module (TIM) When ELSxB:ELSxA = 0:0, this read/write bit selects the initial output level of the TCHx pin. (See 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by ...
Page 141
NOTE: Before enabling a TIM channel register for input capture operation, make sure that the TCHx pin is stable for at least two bus clocks. TOVx — Toggle-On-Overflow Bit When channel output compare channel, this read/write bit ...
Page 142
Timer Interface Module (TIM) 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L) These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers ...
Page 143
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 11. Analog-to-Digital Converter (ADC) 11.1 Contents 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.4.4 11.4.5 11.5 11.6 11.6.1 11.6.2 11.7 11.7.1 11.8 11.8.1 11.8.2 11.8.3 11.2 Introduction This section describes the 12-channel, 8-bit linear successive approximation ...
Page 144
Analog-to-Digital Converter (ADC) 11.3 Features Features of the ADC module include: • 12 channels with multiplexed input • Linear successive approximation with monotonicity • 8-bit resolution • Single or continuous conversion • Conversion complete flag or conversion complete interrupt • ...
Page 145
INTERNAL DATA BUS READ DDRB/DDRD WRITE DDRB/DDRD WRITE PTB/PTD READ PTB/PTD CONVERSION COMPLETE INTERRUPT LOGIC AIEN COCO BUS CLOCK 11.4.1 ADC Port I/O Pins PTB0–PTB7 and PTD0–PTD3 are general-purpose I/O pins that are shared with the ADC channels. The channel ...
Page 146
Analog-to-Digital Converter (ADC) Writes to the port register or DDR will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a ...
Page 147
Accuracy and Precision The conversion process is monotonic and has no missing codes. 11.5 Interrupts When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC conversion. A CPU interrupt is ...
Page 148
Analog-to-Digital Converter (ADC) 11.7.1 ADC Voltage In (ADCVIN) ADCVIN is the input voltage signal from one of the 12 ADC channels to the ADC module. 11.8 I/O Registers These I/O registers control and monitor ADC operation: • ADC status and ...
Page 149
AIEN — ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when the data register is read or the status/control register is written. Reset ...
Page 150
Analog-to-Digital Converter (ADC) ADCH4 ADCH3 ADCH2 ...
Page 151
ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes. Address: Read: Write: Reset: 11.8.3 ADC Input Clock Register This register selects the clock frequency for the ADC. Address: Read: ...
Page 152
Analog-to-Digital Converter (ADC) ADIV2 don’t care Technical Data 152 Table 11-2. ADC Clock Divide Ratio ADIV1 ADIV0 MC68H(R)C908JL3E/JK3E/JK1E Analog-to-Digital Converter (ADC) ADC Clock ...
Page 153
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 12.1 Contents 12.2 12.3 12.3.1 12.3.2 12.3.3 12.4 12.4.1 12.4.2 12.5 12.5.1 12.5.2 12.5.3 12.2 Introduction Twenty three (23) bidirectional input-output (I/O) pins form three parallel ports. All I/O pins are programmable as inputs or outputs. ...
Page 154
Input/Output (I/O) Ports Addr. Register Name Read: Port A Data Register $0000 Write: (PTA) Reset: Read: Port B Data Register $0001 Write: (PTB) Reset: Read: Port D Data Register $0003 Write: (PTD) Reset: Read: Data Direction Register A $0004 Write: ...
Page 155
Table 12-1. Port Control Register Bits Summary Port Bit DDR 0 DDRA0 1 DDRA1 2 DDRA2 3 DDRA3 A 4 DDRA4 5 DDRA5 6 DDRA6 0 DDRB0 1 DDRB1 2 DDRB2 3 DDRB3 B 4 DDRB4 5 DDRB5 6 DDRB6 ...
Page 156
Input/Output (I/O) Ports 12.3 Port A Port 7-bit special function port that shares all seven of its pins with the keyboard interrupt (KBI) module (see Interrupt Module pull-up device if the corresponding port pin is configured as ...
Page 157
Data Direction Register A (DDRA) Data direction register A determines whether each port A pin is an input or an output. Writing a logic one to a DDRA bit enables the output buffer for the corresponding port A pin; ...
Page 158
Input/Output (I/O) Ports When DDRAx is a logic 1, reading address $0000 reads the PTAx data latch. When DDRAx is a logic 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, ...
Page 159
Table 12-2 DDRA PTAPUE Bit PTA Bit Bit Notes Don’t care. 2. I/O pin pulled internal pull-up Writing affects data register, but does not affect input. ...
Page 160
Input/Output (I/O) Ports ADC[7:0] — ADC channels ADC[7:0] are pins used for the input channels to the analog-to-digital converter module. The channel select bits, ADCH[4:0], in the ADC status and control register define which port pin will ...
Page 161
When DDRBx is a logic 1, reading address $0001 reads the PTBx data latch. When DDRBx is a logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the ...
Page 162
Input/Output (I/O) Ports 12.5.1 Port D Data Register (PTD) The port D data register contains a data latch for each of the eight port D pins. Address: Read: Write: Reset: Additional Functions PTD[7:0] — Port D Data Bits These read/write ...
Page 163
Data Direction Register D (DDRD) Data direction register D determines whether each port D pin is an input or an output. Writing a logic one to a DDRD bit enables the output buffer for the corresponding port D pin; ...
Page 164
Input/Output (I/O) Ports When DDRDx is a logic 1, reading address $0003 reads the PTDx data latch. When DDRDx is a logic 0, reading address $0003 reads the voltage level on the pin. The data latch can always be written, ...
Page 165
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 13.1 Contents 13.2 13.3 13.4 13.4.1 13.5 13.6 13.2 Introduction The IRQ (external interrupt) module provides a maskable interrupt input. 13.3 Features Features of the IRQ module include the following: MC68H(R)C908JL3E/JK3E/JK1E MOTOROLA Section 13. External Interrupt ...
Page 166
External Interrupt (IRQ) 13.4 Functional Description A logic zero applied to the external interrupt pin can latch a CPU interrupt request. Interrupt signals on the IRQ1 pin are latched into the IRQ1 latch. An interrupt latch remains set until one ...
Page 167
NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt Exception ACK1 RESET VECTOR FETCH DECODER V DD IRQPUD I NTERNAL PULLUP DEVICE IRQ1 Addr. Register Name Read: IRQ Status and Control ...
Page 168
External Interrupt (IRQ) • Vector fetch or software clear — A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a logic one to the ACK1 bit in the ...
Page 169
IRQ Module During Break Interrupts The system integration module (SIM) controls whether the IRQ1 latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during ...
Page 170
External Interrupt (IRQ) IRQF1 — IRQ1 Flag This read-only status bit is high when the IRQ1 interrupt is pending IRQ1 interrupt pending 0 = IRQ1 interrupt not pending ACK1 — IRQ1 Interrupt Request Acknowledge Bit Writing a logic ...
Page 171
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 14. Keyboard Interrupt Module (KBI) 14.1 Contents 14.2 14.3 14.4 14.4.1 14.4.2 14.4.3 14.5 14.5.1 14.5.2 14.6 14.2 Introduction The keyboard interrupt module (KBI) provides seven independently maskable external interrupts which are accessible via PTA0–PTA6 ...
Page 172
Keyboard Interrupt Module (KBI) Addr. Register Name Read: Keyboard Status $001A and Control Register Write: (KBSCR) Reset: Read: Keyboard Interrupt $001B Enable Register Write: (KBIER) Reset: Figure 14-1. KBI I/O Register Summary 14.4 Functional Description KBI0 . KBIE0 . TO ...
Page 173
A keyboard interrupt is latched when one or more keyboard pins goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. • • If the MODEK ...
Page 174
Keyboard Interrupt Module (KBI) If the MODEK bit is clear, the keyboard interrupt pin is falling-edge- sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and ...
Page 175
Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate 2. Write logic 1s to the appropriate ...
Page 176
Keyboard Interrupt Module (KBI) ACKK — Keyboard Acknowledge Bit Writing a logic 1 to this write-only bit clears the keyboard interrupt request on port-A. ACKK always reads as logic 0. Reset clears ACKK. IMASKK— Keyboard Interrupt Mask Bit Writing a ...
Page 177
Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. 14.5.1 Wait Mode The keyboard modules remain active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables ...
Page 178
Keyboard Interrupt Module (KBI) Technical Data 178 MC68H(R)C908JL3E/JK3E/JK1E Keyboard Interrupt Module (KBI) Rev. 2.0 — MOTOROLA ...
Page 179
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E Section 15. Computer Operating Properly (COP) 15.1 Contents 15.2 15.3 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 15.5 15.6 15.7 15.8 15.8.1 15.8.2 15.9 15.2 Introduction The computer operating properly (COP) module contains a free-running ...
Page 180
Computer Operating Properly (COP) 15.3 Functional Description Figure 15-1 2OSCOUT (1) INTERNAL RESET SOURCES RESET VECTOR FETCH COPCTL WRITE COPEN (FROM SIM) COPD (FROM CONFIG1) RESET COPCTL WRITE COP RATE SEL (COPRS FROM CONFIG1) NOTE: 1. See SIM section for ...
Page 181
NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low for 32 × 2OSCOUT cycles and ...
Page 182
Computer Operating Properly (COP) 15.4.5 Reset Vector Fetch A reset vector fetch occurs when the vector address appears on the data bus. A reset vector fetch clears the SIM counter. 15.4.6 COPD (COP Disable) The COPD signal reflects the state ...
Page 183
COP Control Register The COP control register is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte ...
Page 184
Computer Operating Properly (COP) 15.8.2 Stop Mode Stop mode turns off the 2OSCOUT input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period ...
Page 185
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 16.1 Contents 16.2 16.3 16.4 16.5 16.6 16.6.1 16.6.2 16.2 Introduction This section describes the low-voltage inhibit module (LVI), which monitors the voltage on the V voltage falls to the LVI trip (LVI 16.3 Features Features ...
Page 186
Low Voltage Inhibit (LVI) 16.4 Functional Description Figure 16-1 after a reset. The LVI module contains a bandgap reference circuit and comparator. Setting LVI disable bit (LVID) disables the LVI to monitor V voltage. The LVI trip voltage selection bits ...
Page 187
Address: Read: Write: Reset: LVID — Low Voltage Inhibit Disable Bit LVIT1, LVIT0 — LVI Trip Voltage Selection These two bits determine at which level of V come into action. LVIT1 and LVIT0 are cleared by a Power-On Reset only. ...
Page 188
Low Voltage Inhibit (LVI) Technical Data 188 MC68H(R)C908JL3E/JK3E/JK1E Low Voltage Inhibit (LVI) Rev. 2.0 — MOTOROLA ...
Page 189
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 17.1 Contents 17.2 17.3 17.4 17.4.1 17.4.2 17.4.3 17.4.4 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.6 17.6.1 17.6.2 17.2 Introduction This section describes the break module. The break module can generate a break interrupt that stops normal ...
Page 190
Break Module (BREAK) 17.3 Features Features of the break module include the following: • Accessible I/O registers during the break Interrupt • CPU-generated break interrupts • Software-generated break interrupts • COP disabling during break interrupts 17.4 Functional Description When the ...
Page 191
Addr. Register Name Read: Break Status Register $FE00 Write: (BSR) Reset: Read: Break Flag Control $FE03 Register Write: (BFCR) Reset: Read: Break Address High $FE0C Register Write: (BRKH) Reset: Read: Break Address low $FE0D Register Write: (BRKL) Reset: Read: Break ...
Page 192
Break Module (BREAK) 17.4.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software ...
Page 193
Break Status and Control Register (BRKSCR) The break status and control register contains break module enable and status bits. Address: Read: Write: Reset: BRKE — Break Enable Bit This read/write bit enables breaks on break address register matches. Clear ...
Page 194
Break Module (BREAK) 17.5.2 Break Address Registers The break address registers contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers. Address: Read: Write: Reset: Address: Read: Write: Reset: 17.5.3 Break Status Register ...
Page 195
SBSW — SIM Break Stop/Wait This status bit is useful in applications requiring a return to wait or stop mode after exiting from a break interrupt. Clear SBSW by writing a logic zero to it. Reset clears SBSW. SBSW can ...
Page 196
Break Module (BREAK) 17.5.4 Break Flag Control Register (BFCR) The break control register contains a bit that enables software to clear status bits while the MCU break state. Address: Bit 7 Read: BCFE Write: Reset: BCFE — ...
Page 197
Technical Data – MC68H(R)C908JL3E/JK3E/JK1E 18.1 Contents 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . ...
Page 198
Electrical Specifications 18.3 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to Sections conditions. ...
Page 199
Functional Operating Range Operating temperature range Operating voltage range 18.5 Thermal Characteristics Thermal resistance I/O pin power dissipation Power dissipation Constant Average junction temperature NOTES: 1. Power dissipation is a function of temperature constant unique to the ...
Page 200
Electrical Specifications 18 Electrical Characteristics Table 18-4. DC Electrical Characteristics (5V) (1) Characteristic Output high voltage (I = –2.0mA) LOAD PTA0–PTA6, PTB0–PTB7, PTD0–PTD7 Output low voltage (I = 1.6mA) LOAD PTA6, PTB0–PTB7, PTD0, PTD1, PTD4, PTD5 Output low ...