M66222FP MITSUBISHI [Mitsubishi Electric Semiconductor], M66222FP Datasheet

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M66222FP

Manufacturer Part Number
M66222FP
Description
128 x 8-BIT x 2 MAIL-BOX
Manufacturer
MITSUBISHI [Mitsubishi Electric Semiconductor]
Datasheet

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Part Number
Manufacturer
Quantity
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Part Number:
M66222FP
Manufacturer:
MIT
Quantity:
5 510
Part Number:
M66222FP
Manufacturer:
MIT
Quantity:
20 000
DESCRIPTION
The M66222 is a mail box that incorporates two complete CMOS
shared memory cells of 128
performance silicon gate CMOS process technology, and are
equipped with two access ports of A and B.
Access ports A and B are equipped with independent addresses CS,
WE and OE control pins and I/O pins to allow independent and
asynchronous read/write operations individually. This product
exclusively performs a write operation from A port and a read operation
from B port for one memory, and a read operation from A port and a
write operation from B port for the other memory.
FEATURES
• Memory configuration of 128
• High-speed access, address access time 40ns (typ.)
• Complete asynchronous accessibility from ports A and B
• Fixed read/write access ports for memory
• Completely static operation
• Low power dissipation CMOS design
• 5V single power supply
• TTL direct-coupled I/O
• 3-state output for I/O pins
APPLICATION
Inter-MCU data transfer memory, communication buffer memory
BLOCK DIAGRAM
CHIP SELECT
INPUT
WRITE
ENABLE INPUT
OUTPUT
ENABLE INPUT
A PORT
ADDRESS
INPUT
A PORT
DATA I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WEA
OEA
CSA
A
A
A
A
A
A
A
A
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
12
10
11
13
14
15
16
17
18
19
20
1
2
4
5
6
7
8
9
CONTROL
CIRCUIT
WRITE
READ/
7
8 bits
8-bit configuration using high-
2 memory areas
A
0
A~A
Write
Read
6
A
MEMORY AREA(1)
128-WORD 8-BIT
CONFIGURATION
MEMORY AREA(2)
128-WORD 8-BIT
CONFIGURATION
ADDRESSES
ROW/COLUMN
ROW/COLUMN
ADDRESSES
DECODER
DECODER
128-255
0-127
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
OUTPUT ENABLE
INPUT
PIN CONFIGURATION (Top view)
A PORT
ADDRESS
INPUT
A PORT
DATA I/O
Read
Write
A
0
B~A
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
WEA
GND
B
OEA
CSA
A
A
A
A
A
A
A
A
NC
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
M66222SP/FP
Outline
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
MITSUBISHI DIGITAL ASSP
42
21
MITSUBISHI DIGITAL ASSP
V
CONTROL
GND
CIRCUIT
WRITE
READ/
CC
128
42P4B
42P2R-A
7
128
M66222SP/FP
8-BIT
41
40
38
30
37
36
35
34
33
32
31
22
23
24
25
26
27
28
29
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CSB
WEB
OEB
A
A
A
A
A
A
I/O
8-BIT
7
0
1
2
3
4
5
6
B
B
B
B
B
B
B
B
0
1
2
3
4
5
6
V
CSB
WEB
NC
OEB
A
A
A
A
A
A
A
A
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
NC: No Connection
B
B
B
B
B
B
B
B
CC
0
1
2
3
4
5
6
7
B
B
B
B
B
B
B
B
2 MAIL-BOX
7
6
5
4
3
2
1
0
CHIP
SELECT INPUT
WRITE
ENABLE INPUT
OUTPUT
ENABLE INPUT
B
B
B
B
B
B
B
B
CHIP SELECT
INPUT
WRITE ENABLE
INPUT
OUTPUT ENABLE
INPUT
B PORT
ADDRESS
INPUT
B PORT
DATA I/O
2 MAIL-BOX
B PORT
ADDRESS
INPUT
B PORT
DATA I/O
1

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M66222FP Summary of contents

Page 1

DESCRIPTION The M66222 is a mail box that incorporates two complete CMOS shared memory cells of 128 8-bit configuration using high- performance silicon gate CMOS process technology, and are equipped with two access ports of A and B. Access ports ...

Page 2

FUNCTION The M66222 is a mail box most suitable for inter-MCU data communication interface. Provision of two pairs of addresses and data buses in its shared memory cell of 128 allows independent and asynchronous read/write operations from/to two access ports ...

Page 3

FUNCTIONAL DESCRIPTION The M66222 with independent and asynchronous accessibility from two ports has the following four basic operations depending on an address and mode set from both ports: (1) A port .......... Write B port .......... Write (2) A port ...

Page 4

ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply voltage CC V Input voltage I V Output voltage O P Maximum power dissipation d T Storage temperature range stg RECOMMENDED OPERATING CONDITIONS Symbol Parameter V Supply voltage CC GND Ground V Input ...

Page 5

SWITCHING CHARACTERISTICS Read cycle Symbol t Read cycle time CR t Address access time a(A) t Chip select access time a(CS) t Output enable access time a(OE) t Output disable time after CS (Note 5) dis(CS) t Output disable time ...

Page 6

TIMING DIAGRAM Read Cycle ( Read cycle No. 1 (Address control) ( I/O ~I/O Previous cycle data OUT Read cycle No. 2 (CS control) ...

Page 7

Write Cycle Write cycle No.1 (WE control) See Notes 6, 7 and su(A)1 WE I/O ~I I/O ~I OUT Write cycle No.2 (CS ...

Page 8

SWITCHING CHARACTERISTICS MEASUREMENT CIRCUIT Input pulse level : V = 3.0V Input pulse rise/fall time : 5ns r f Input timing reference voltage : 1.5V Output timing decision voltage : 1.5V Output load : Figure ...

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