AT89C2051X2 ATMEL [ATMEL Corporation], AT89C2051X2 Datasheet
AT89C2051X2
Related parts for AT89C2051X2
AT89C2051X2 Summary of contents
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... RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C2051x2 is designed with static logic for oper- ation down to zero frequency and supports two software selectable power saving modes ...
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... Block Diagram AT89C2051x2 2 3285B–MICRO–10/03 ...
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... Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I because of the pull-ups. Port 3 also serves the functions of various special features of the AT89C2051x2 as listed below: Port Pin Alternate Functions P3 ...
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... Oscillator Characteristics X2 Mode Description AT89C2051x2 4 XTAL1 and XTAL2 are the input and output, respectively inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. ...
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... User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0. Table 1. AT89C2051x2 SFR Map and Reset Values 0F8H 0F0H B ...
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... The AT89C2051x2 contains 128 bytes of internal data memory. Thus, in the AT89C2051x2, the stack depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is not supported in this device, nor is external PRO- GRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program ...
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... P1.0 and P1.1 should be set to “0” external pull-ups are used, or set to “1” if external pull-ups are used. The AT89C2051x2 is shipped with the 2K bytes of on-chip Flash code memory array in the erased state (i.e., contents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the array is programmed, to re-program any non-blank byte, the entire memory array needs to be erased electrically ...
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... Turn V power off CC Data Polling: The AT89C2051x2 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written data on P1.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated ...
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... The internal memory address counter is reset to 000H on the rising edge of RST and is advanced by a positive pulse at XTAL1 pin. 2. Chip Erase requires PROG pulse. 3. P3.1 is pulled Low during programming to indicate RDY/BSY. 3285B–MICRO–10/03 RST/VPP P3.2/PROG 12V H H Bit - 1 12V Bit - 2 12V 12V H H AT89C2051x2 P3.3 P3.4 P3 ...
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... Figure 4. Programming the Flash Memory RDY/BSY PROG SEE FLASH PROGRAMMING MODES TABLE TO INCREMENT ADDRESS COUNTER Figure 5. Verifying the Flash Memory V IH SEE FLASH PROGRAMMING MODES TABLE 4.5V - 5.5V AT89C2051x2 V CC PGM P3.2 P1 DATA P3.3 P3.4 P3.5 P3 XTAL1 RST IH PP GND 4.5V - 5.5V AT89C2051x2 V CC PGM P3.2 P1 DATA P3.3 P3.4 P3.5 P3.7 XTAL1 V RST IH GND 3285B–MICRO–10/03 ...
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... PROG High to BUSY Low GHBL t Byte Write Cycle Time WC t RDY/BSY\ to Increment Clock Delay BHIH t Increment Clock High IHIL Note: 1. Only used in 12-volt programming mode. Flash Programming and Verification Waveforms 3285B–MICRO–10/03 PP AT89C2051x2 Min Max Units 11.5 12.5 V 250 µA 1.0 µs 1.0 µs 1.0 µs 10 µ ...
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... Under steady state (non-transient) conditions, I Maximum I per port pin Maximum total I for all output pins exceeds the test condition than the listed test conditions. 2. Minimum V for Power-down is 2V. CC AT89C2051x2 12 *NOTICE: Condition (Except XTAL1, RST) (XTAL1, RST mA mA 2.7V ...
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External Clock Drive Waveforms External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL t /t Cyclic Ratio (duty cycle) CHCX ...
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... V max. for a logic 0. IL (1) Float Waveforms Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded V AT89C2051x2 MHz Osc Min 1.0 700 50 ...
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... 1.5 FREQUENCY (MHz) AT89C2051x2 TYPICAL ICC vs. VOLTAGE - POWER DOWN (85˚ µ 3.0V 4.0V Vcc VOLTAGE Notes: 1. XTAL1 tied to GND for P.1.0 and P1 GND Lock bits programmed. AT89C2051x2 Vcc=6.0V Vcc=5.0V Vcc=3. Vcc=6.0V Vcc=5.0V Vcc=3.0V 3 4.5 6 5.0V 6.0V (power-down). 15 ...
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... Supply Ordering Code 8 2.7V to 6.0V AT89C2051x2-8PC AT89C2051x2-8SC AT89C2051x2-8PI AT89C2051x2-8SI 16 4.0V to 6.0V AT89C2051x2-16PC AT89C2051x2-16SC AT89C2051x2-16PI AT89C2051x2-16SI 20P3 20-lead, 0.300” Wide, Plastic Dual In-line Package (PDIP) 20S2 20-lead, 0.300” Wide, Plastic Gull Wing Small Outline (SOIC) AT89C2051x2 16 Package 20P3 20S2 20P3 20S2 ...
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... Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 3285B–MICRO–10/03 D PIN TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) AT89C2051x2 E1 A1 COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM A – – A1 0.381 – D 25.984 – ...
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... The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.024") per side. 2325 Orchard Parkway San Jose, CA 95131 R AT89C2051x2 SYMBOL ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...