AT89C51CC02CA-TDSUM ATMEL [ATMEL Corporation], AT89C51CC02CA-TDSUM Datasheet
AT89C51CC02CA-TDSUM
Manufacturer Part Number
AT89C51CC02CA-TDSUM
Description
Enhanced 8-bit Microcontroller with CAN Controller and Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT89C51CC02CA-TDSUM.pdf
(156 pages)
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Note:
80C51 Core Architecture
256 Bytes of On-chip RAM
256 Bytes of On-chip XRAM
16K Bytes of On-chip Flash Memory
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
Three or Four Ports: 16 or 20 Digital I/O Lines
Two-channel 16-bit PCA
Double Data Pointer
21-bit Watchdog Timer (7 Programmable bits)
A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller
1-Mbit/s Maximum Transfer Rate at 8 MHz
Readable Error Counters
Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
Independent Baud Rate Prescaler
Data, Remote, Error and Overload Frame Handling
Power-saving Modes
Power Supply: 3 Volts to 5.5 Volts
Temperature Range: Industrial (-40° to +85°C)
Packages: SOIC28, SOIC24, PLCC28, VQFP32
– Data Retention: 10 Years at 85°C
– Erase/Write Cycle: 100K
– Erase/Write Cycle: 100K
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
– Fully Compliant with CAN rev.# 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 4 Independent Message Objects
– Supports
– Idle Mode
– Power-down Mode
1. At BRP = 1 sampling point will be fixed.
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Register (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
-Access to Message Object Control and Data Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects
Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
(1)
Crystal Frequency In X2 Mode
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash
T89C51CC02
AT89C51CC02
Rev. 4126J–CAN–05/06
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