ISL6334 INTERSIL [Intersil Corporation], ISL6334 Datasheet

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... This improves regulation and protection accuracy. The threshold-sensitive enable input is available to accurately coordinate the start-up of the ISL6334, ISL6334A with any other voltage rail. Dynamic-VID™ technology allows seamless on-the-fly VID changes. The offset pin allows accurate voltage offset settings that are independent of VID setting ...

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... ISL6334 IRZ ISL6334AIRZ* 6334A IRZ ISL6334CRZ* ISL6334 CRZ ISL6334ACRZ* 6334A CRZ *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations ...

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... ISL6610, ISL6610A 5V Quad NOTE: Note: Intersil 5V and 12V drivers are mostly pin-to-pin compatible and allow dual footprint layout to optimize MOSFET selection and efficiency. Dual = One Synchronous Channel; Quad = Two Synchronous Channels. 3 ISL6334, ISL6334A COMMENTS DIODE GATE DRIVE EMULATION DROP (DE) ...

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... ISL6334 and ISL6334A Block Diagram VDIFF - RGND X1 + VSEN SOFT-START + OVP - FAULT LOGIC +175mV SS VID7 VID6 VID5 DYNAMIC VID4 VID VID3 D/A VID2 VID1 VID0 DAC OFS OFFSET REF FB COMP 1.11V + OCP - IMON 1.11V VR_HOT THERMAL MONITOR VR_FAN TM 4 ISL6334, ISL6334A VR_RDY FS PSI# ...

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... PWM3 ISEN3- VR_HOT VIN ISEN3+ EN_PWR +5V GND PWM4 IMON ISEN4- ISEN4+ TCOMP TM OFS FS +5V +5V NTC NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 5 ISL6334, ISL6334A +12V PVCC VCC ISL6622 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V SS PVCC ...

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... ISEN3- VR_HOT ISEN3+ VIN EN_PWR +5V GND PWM4 ISEN4- IMON ISEN4+ TCOMP TM OFS FS +5V +5V NTC NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 6 ISL6334, ISL6334A +12V PVCC VCC ISL6612 DRIVER PWM DAC REF +12V PVCC VCC ISL6612 DRIVER PWM +12V PVCC VCC ISL6612 DRIVER PWM +12V ...

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... VR_FAN ISEN2- VR_HOT PWM2 VIN EN_PWR PWM4 +5V GND ISEN4- ISEN4+ IMON TCOMP TM OFS FS +5V NTC 5V NTC: NTHS0805N02N6801, 6.8kΩ, VISHAY 7 ISL6334, ISL6334A +12V VCC DAC GND REF ISL6614 DRIVER PWM1 PWM2 +12V VCC GND ISL6614 DRIVER SS PWM1 5V PWM2 VIN BOOT1 UGATE1 PHASE1 ...

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... Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Ambient Temperature ISL6334ACRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C ISL6334CRZ 0°C to +70°C Ambient Temperature ISL6334IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C ISL6334AIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty ...

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... Overcurrent Trip Level for Average Current At Normal CCM PWM Mode Overcurrent Trip Level for Average Current at PSI# Mode Peak Current Limit for Individual Channel IMON Clamped and OCP Trip Level 9 ISL6334, ISL6334A TEST CONDITIONS (Note 4) Offset resistor connected to ground Voltage below VCC, offset resistor connected to VCC R = 100kΩ ...

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... Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle. 7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 10 ISL6334, ISL6334A TEST CONDITIONS With external pull-up resistor connected to VCC With 1.24k resistor pull-up to VCC, I ...

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... It’s typically connected to VTT output of VTT voltage regulator in the computer mother board. When EN_VTT is driven above 0.875V, the ISL6334, ISL6334A is active depending on status of the EN_PWR, the internal POR, and pending fault states. Driving EN_VTT below 0.745V will clear all fault states and prime the ISL6334, ISL6334A to soft-start when re-enabled ...

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... The ISL6334, ISL6334A controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. The block diagrams on pages page 5, 7, and 6 provide top level views of multiphase power conversion using the ISL6334, ISL6334A controller ...

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... PWM and PSI# Operation The timing of each channel is set by the number of active channels. The default channel setting for the ISL6334, ISL6334A is four. The switching cycle is defined as the time between PWM pulse termination signals of each channel. The cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the FS pin and ground ...

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... PWM protocol that the dedicated VR11.1 drivers can decode and then enter diode emulation mode with gate drive voltage optimization. The ISL6334A only generates 2-level normal CCM PWM except for faults. No dedicated VR11.1 driver is required. See “Controller and Driver Recommendation” on page 3. ...

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... The sensed average current I This current will develop voltage drop across the resistor between FB and VDIFF pins for droop control. ISL6334, ISL6334A can not be used for non-droop applications. The output of the error amplifier, V sawtooth waveforms to generate the PWM signals. The ...

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... OUT FIGURE 6. OUTPUT VOLTAGE AND LOAD-LINE REGULATION WITH OFFSET ADJUSTMENT The ISL6334, ISL6334A incorporates an internal differential remote-sense amplifier in the feedback path. The amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point, resulting in a more accurate means of sensing output voltage ...

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... ISL6334, ISL6334A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 1 0 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 ...

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... ISL6334, ISL6334A VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 VOLTAGE 1 0 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 ...

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... OFS logic high. OFS Enable and Disable While in shutdown mode, the PWM outputs are held in a high-impedance state to assure the drivers remain off. The following input conditions must be met before the ISL6334, ISL6334A is released from shutdown mode. : OFS to VCC): OFS × ...

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... Vboot voltage. Then, the controller will regulate the VR voltage at 1.1V for another fixed period t ISL6334A reads the VID signals. If the VID code is valid, ISL6334, ISL6334A will initiate the second soft-start ramp until the voltage reaches the VID voltage minus offset voltage. ...

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... When the output voltage at VSEN is below the undervoltage threshold, VR_RDY is pulled low. Overvoltage Protection Regardless of the VR being enabled or not, the ISL6334, ISL6334A overvoltage protection (OVP) circuit will be active after its POR. The OVP thresholds are different under different operation conditions. When VR is not enabled and ...

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... If one channel current exceeds the reference current, ISL6334, ISL6334A will pull PWM signal of this channel to low for the rest of the switching cycle. This PWM signal can be turned on next cycle if the sensed channel current is less than the 129µ ...

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... Therefore the TM voltage can be utilized to obtain the temperature of the current sense component. (EQ. 19) Based on VCC voltage, ISL6334, ISL6334A converts the TM pin voltage to a 6-bit TM digital signal for temperature compensation. With the non-linear A/D converter of (EQ. 20) ISL6334, ISL6334A, the TM digital signal is linearly proportional to the NTC temperature ...

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... VDIFF pins reverse proportional to the temperature. The external temperature compensation network can only (EQ. 21) compensate the temperature impact on the droop, while it has no impact to the sensed current inside ISL6334, ISL6334A. Therefore, this network cannot compensate for the temperature impact on the overcurrent protection function. (EQ. 22) ...

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... Upper MOSFET losses can be divided into separate components involving the upper-MOSFET switching times; 25 ISL6334, ISL6334A the lower-MOSFET body-diode reverse-recovery charge, Q and the upper MOSFET r When the upper MOSFET turns off, the lower MOSFET does not conduct any portion of the inductor current until the voltage at the phase node falls below ground ...

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... I is the full load current of the specific application, FL and VR is the desired voltage droop under the full DROOP load condition. 26 ISL6334, ISL6334A can be chosen Based on the desired loadline R OCP resistor can be calculated using Equation 33 where N is the active channel number, R ...

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... DROOP - VDIFF FIGURE 17. COMPENSATION CONFIGURATION FOR LOAD-LINE REGULATED ISL6334, ISL6334A CIRCUIT The feedback resistor has already been chosen as FB outlined in “Load-Line Regulation Resistor” on page 26. Select a target bandwidth for the compensated system, f The target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency ...

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... MOSFETs. Their RMS current capacity must be sufficient to handle the AC component of the current drawn by the upper MOSFETs which is related to duty cycle and the number of active phases. 28 ISL6334, ISL6334A (EQ. 37) FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS CURRENT (EQ. 38) FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT (EQ. 39) ⎞ ...

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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 29 ISL6334, ISL6334A Layout Considerations O The following layout strategies are intended to minimize the ...

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... L40.6x6 40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 3, 10/06 6.00 6 PIN 1 INDEX AREA (4X) 0.15 TOP VIEW ( TYP ) ( TYPICAL RECOMMENDED LAND PATTERN 30 ISL6334, ISL6334A 4X 36X 0. 40X ± BOTTOM VIEW ± SIDE VIEW ( 36X REF ( 40X 0 ...