ISL6537 INTERSIL [Intersil Corporation], ISL6537 Datasheet

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ISL6537

Manufacturer Part Number
ISL6537
Description
ACPI Regulator/Controller for Dual Channel DDR Memory Systems
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet

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ACPI Regulator/Controller for
Dual Channel DDR Memory Systems
The ISL6537 provides a complete ACPI compliant power
solution for up to 4 DIMM dual channel DDR/DDR2 Memory
systems. Included are both a synchronous buck controller to
supply V
state, a fully integrated sink-source regulator generates an
accurate (V
need for a negative supply. A buffered version of the V
reference is provided as V
integrated for the GMCH core voltage regulation and for the
GMCH and CPU V
The switching PWM controller drives two N-Channel
MOSFETs in a synchronous-rectified buck converter
topology. The synchronous buck converter uses voltage-
mode control with fast transient response. The switching
regulator provides a maximum static regulation tolerance of
±
user-adjustable by means of external resistors down to 0.8V.
An integrated soft-start feature brings all outputs into
regulation in a controlled manner when returning to S0/S1
state from any sleep state. During S0 the VIDPGD signal
indicates that the GMCH and CPU V
is within spec and operational.
Each output is monitored for undervoltage events. The
switching regulator also has overvoltage and overcurrent
protection. Thermal shutdown is integrated.
Pinout
2% over line, load, and temperature ranges. The output is
DDR_VTT
DDR_VTT
5VSBY
VDDQ
P12V
GND
S3#
DDQ
DDQ
1
2
3
4
5
6
7
during S0/S1 and S3 states. During S0/S1
/2) high current V
28
8
TT
27
9
ISL6537 (6x6 QFN)
termination voltage regulation.
10
26
TOP VIEW
REF
®
GND
11
25
29
. Two LDO controllers are also
1
TT
12
24
Data Sheet
voltage without the
TT
13
23
termination voltage
14
22
21
20
19
18
17
16
15
DRIVE4
REFADJ4
DRIVE3
FB3
FB4
COMP
FB
DDQ
1-888-INTERSIL or 1-888-468-3774
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
/2
Features
• Generates 4 Regulated Voltages
• ACPI Compliant Sleep State Control
• Glitch-free Transitions During State Changes
• Integrated V
• PWM Controller Drives Low Cost N-Channel MOSFETs
• 250kHz Constant Frequency Operation
• Tight Output Voltage Regulation
• Fully-Adjustable Outputs with Wide Voltage Range: Down
• Simple Single-Loop Voltage-Mode PWM Control Design
• Fast PWM Converter Transient Response
• Under and Overvoltage Monitoring on All Outputs
• OCP on the Switching Regulator
• Integrated Thermal Shutdown Protection
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Single and Dual Channel DDR Memory Power Systems in
• Graphics Cards - GPU and Memory Supplies
• ASIC Power Supplies
• Embedded Processor and I/O Supplies
• DSP Supplies
Ordering Information
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
ISL6537CR
ISL6537CRZ
(See Note)
NUMBER
- Synchronous Buck PWM Controller for DDR V
- 3A Integrated Sink/Source Linear Regulator with
- LDO Regulator for GMCH Core
- LDO Regulator for CPU/GMCH V
- All Outputs:
to 0.8V supports DDR and DDR2 Specifications
ACPI Compliant PCs
PART
Accurate VDDQ/2 Divider Reference for DDR V
All other trademarks mentioned are the property of their respective owners.
July 18, 2007
Copyright © Intersil Americas Inc. 2004, 2005, 2007. All Rights Reserved
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
ISL6537CR
ISL6537CRZ
MARKING
REF
PART
±
2% Over Temperature
Buffer
RANGE (°C)
0 to +70
0 to +70
TEMP.
TT
28 Ld 6x6 QFN L28.6x6
28 Ld 6x6 QFN
(Pb-free)
PACKAGE
Termination
ISL6537
FN9142.6
DDQ
TT
DWG. #
L28.6x6
PKG.

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ISL6537 Summary of contents

Page 1

... Data Sheet ACPI Regulator/Controller for Dual Channel DDR Memory Systems The ISL6537 provides a complete ACPI compliant power solution for DIMM dual channel DDR/DDR2 Memory systems. Included are both a synchronous buck controller to supply V during S0/S1 and S3 states. During S0/S1 DDQ state, a fully integrated sink-source regulator generates an ...

Page 2

Block Diagram VDDQ P12V R GU EA4 DRIVE4 GMCH DUAL LDO R GL FB4 REFADJ4 P12V EA3 DRIVE3 FB3 P12V EA2 DRIVE2 FB2 5VSBY P12V S3# S5# FB POR MONITOR AND CONTROL FAULT SOFT-START & ENABLE A SOFT-START & ENABLE ...

Page 3

... SLEEP STATE LOGIC PWM CONTROLLER TWO STAGE LINEAR CONTROLLER ISL6537 VTT LINEAR REGULATOR CONTROLLER 5VSBY 12V BOOT VIDPGD S5# OCSET S3# ISL6537 DRIVE4 UGATE FB4 PHASE REFADJ4 LGATE DRIVE3 DDR_VDDQ(x2) COMP FB3 R6 FB DRIVE2 VREF_OUT FB2 VREF_IN R8 DDR_VTT(x2) GND DDR_VTTSNS 5VDUAL ...

Page 4

... DC Gain Gain-Bandwidth Product Slew Rate CONTROL I/O (S3# and S5#) Low Level Input Threshold High Level Input Threshold 4 ISL6537 Thermal Information Thermal Resistance QFN Package (Notes Maximum Junction Temperature (Plastic Package +150° 7.0V (DC) Maximum Storage Temperature Range . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www ...

Page 5

... ISL6537 SYMBOL TEST CONDITIONS I GATE I GATE VREF_OUT I Periodic load applied with 30% duty cycle VTT_MAX and 10ms period using ISL6537_6506EVAL1 evaluation board (see Application Note AN1123) (Note 3) GBWP (Note 3) SR (Note 3) DRIVEn unloaded V = 770mV DRIVEn V = 830mV DRIVEn S0 S0 ...

Page 6

... Functional Pin Description 5VSBY (Pin 1) 5VSBY is the bias supply of the ISL6537 typically connected to the 5V standby rail of an ATX power supply. During S4/S5 sleep states the ISL6537 enters a reduced power mode and draws less than 1mA (I 5VSBY supply. The supply to 5VSBY should be locally bypassed using a 0.1μ ...

Page 7

... ISL6537 receives its bias voltage from the 5V Standby bus (5VSBY). Once the 5VSBY rail has exceeded the POR threshold, the ISL6537 will remain in an internal S5 state until both the SLP_S3 and SLP_S5 signal have transitioned high and the 12V POR threshold has been exceeded by the ...

Page 8

... V GMCH 0V V TT_GMCH/CPU 0V VIDPGD (3 SOFTSTART CYCLES Soft-Start Rise Time Dependent Upon Capacitor On V TT_DDR V FLOATING TT_DDR (3 SOFTSTART CYCLES FIGURE 1. ISL6537 TIMING DIAGRAM Pin REF_IN ...

Page 9

... If a fault occurs prior to the Fault Reset Counter reaching a count of 16384, then the Fault Reset Counter is set back to zero. The ISL6537 will immediately shut down when the Fault Counter reaches a count of 4 when the system is restarting from an S5 state into the active, or S0, state. The ISL6537 and the SLP_S3 signal transitions HIGH ...

Page 10

... The 16384 counts that are required to reset the Fault Reset Counter represent 8 soft-start cycles, as one soft-start cycle is 2048 clock cycles. This allows the ISL6537 to attempt at least one full soft-start sequence to restart the faulted regulators. When attempting to restart a faulted regulator, the ISL6537 will follow the preset start up sequencing ...

Page 11

... This allows the heat to move away from the IC and also ties the pad to the ground plane through a low impedance path. The switching components should be placed close to the ISL6537 first. Minimize the length of the connections between the input capacitors and the power switches IN by placing them nearby ...

Page 12

... F ESR = 2π The compensation network consists of the error amplifier (internal to the ISL6537) and the impedance networks Z and Z . The goal of the compensation network is to provide FB a closed loop transfer function with the highest 0dB crossing frequency (f ) and adequate phase margin. Phase margin ...

Page 13

... The output voltage for the internal V TT_DDR is set internal to the ISL6537 to track the V 50%. There is no need for external programming resistors. Component Selection Guidelines Output Capacitor Selection - PWM Buck Converter An output capacitor is required to filter the inductor current and supply the load transient current ...

Page 14

... These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse- recovery of the upper and lower MOSFET’s body diode. The gate-charge losses are dissipated in part by the ISL6537 and do not significantly heat the MOSFETs. However, large gate- charge increases the switching interval, t the MOSFET switching losses ...

Page 15

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 ISL6537 L28.6x6 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220VJJC ISSUE C) ...

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