ISL6530/31EVAL1 INTERSIL [Intersil Corporation], ISL6530/31EVAL1 Datasheet - Page 12

• Manufacturer Part Number: ISL6530/31EVAL1
• Description: Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination
• Manufacturer: INTERSIL [Intersil Corporation]

The compensation network consists of the error amplifier
(internal to the ISL6531) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
Compensation Break Frequency Equations
Figure 9 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 9. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 9 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain..
F
F
1. Pick gain (R
2. Place first zero below filter’s double pole (~75% F
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
3
Z1
Z2
, C
100
-20
-40
-60
80
60
40
20
=
=
0
FB
1
, C
--------------------------------- -
2π
------------------------------------------------------ -
2π x R
. The goal of the compensation network is to provide
10
MODULATOR
20
2
×
log
, and C
0dB
R
GAIN
(
1
2


1
100
×
R2
------- -
R1
) and adequate phase margin. Phase margin
F
2
1
+
C
Z1
/R


R
2
3
3
1
) in Figure 7. Use these guidelines for
) x C
) for desired converter bandwidth.
F
1K
LC
F
FREQUENCY (Hz)
3
Z2
F
ESR
10K
12
F
F
F
P1
P1
P2
P2
100K
=
=
F
with the capabilities of
P2
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
1M
1
ERROR AMP GAIN
2
3
COMPENSATION
x
x C
OPEN LOOP
20
1
LOOP GAIN



C
--------------------- -
10M
C
3
log
GAIN
1
1
LC
+
x C



0dB
--------------- -
V
C
V
).
1
OSC
2
2
IN
, R



and
IN



2
,
ISL6531
The compensation gain uses external impedance networks
Z
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin
V
To ease design and reduce the number of small-signal
components required, the V
compensated. The only stability criteria that needs to be
met relates the minimum value of the inductor to the
equivalent ESR of the output capacitor bank as shown in
the following equation:
where
L
current
ESR
V
The design procedure for this output should follow the
following steps:
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern digital ICs can produce high transient load slew
rates. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
L
1. Choose the number and type of output capacitors to meet
2. Determine the equivalent ESR of the output capacitor
3. Verify that the chosen inductor meets this minimum value
FB
OUT(MIN)
IN
TT
OUT MIN
the output transient requirements based on the dynamic
loading characteristics of the output.
bank and calculate the minimum output inductor value.
criteria at full output load. It is recommended that the
chosen inductor be no more than 30% saturated at full
output load.
= Input voltage of the converter
and Z
OUT
Feedback Compensation
(
= equivalent ESR of the output capacitor bank
IN
)
≥
= minimum output inductor value at full output
to provide a stable, high bandwidth (BW) overall
20
⋅
(
10
–
6
)
×
ESR
TT
OUT
regulator is internally
×
V
IN