ISL6530/31EVAL1 INTERSIL [Intersil Corporation], ISL6530/31EVAL1 Datasheet - Page 6

• Manufacturer Part Number: ISL6530/31EVAL1
• Description: Dual 5V Synchronous Buck Pulse-Width Modulator (PWM) Controller for DDRAM Memory VDDQ and VTT Termination
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Pin Description
BOOT1 and BOOT2
These pins provide bias voltage to the upper MOSFET
drivers. A single capacitor bootstrap circuit may be used to
create a BOOT voltage suitable to drive a standard N-
Channel MOSFET.
UGATE1 and UGATE2
Connect UGATE1 and UGATE2 to the corresponding upper
MOSFET gate. These pins provide the gate drive for the
upper MOSFETs. UGATE2 is also monitored by the adaptive
shoot through protection to determine when the upper FET
of the V
LGATE1 and LGATE2
Connect LGATE1 and LGATE2 to the corresponding lower
MOSFET gate. These pins provide the gate drive for the
lower MOSFETs. These pins are monitored by the adaptive
shoot through protection circuitry to determine when the
lower FET has turned off.
PGND1 and PGND2
These are the power ground connections for the gate drivers
of the PWM controllers. Tie these pins to the ground plane
through the lowest impedence connection available.
OCSET/SD
A resistor (R
the upper MOSFET of the V
overcurrent trip point. R
source (I
TT
OCS
regulator has turned off.
VREF_IN
UGATE2
OCSET
UGATE1
PHASE1
PHASE2
SENSE1
), and the upper MOSFET on-resistance
COMP1
BOOT2
BOOT1
GNDA
VREF
FB1
) connected from this pin to the drain of
10
11
12
1
2
3
4
5
7
8
9
6
24 LEAD (SOIC)
OCSET
TOP VIEW
DDQ
6
, an internal 40µA current
regulator sets the
24
23
22
21
20
19
18
17
16
15
14
13
PGND1
LGATE1
PVCC1
OCSET/SD
V2_SD
PGOOD
N/C
SENSE2
N/C
VCC
LGATE2
PGND2
ISL6531
(r
according to the following equation:
An overcurrent trip cycles the soft-start function.
Pulling the OCSET/SD pin to ground resets the ISL6531 and
all external MOSFETS are turned off allowing the two output
voltage power rails to float.
PGOOD
A high level on this open-drain output indicates that both the
V
voltage ranges.
GNDA
Signal ground for the IC. Tie this pin to the ground plane
through the lowest impedence connection available.
VCC
The 5V bias supply for the chip is connected to this pin. This
pin is also the positive supply for the lower gate driver,
LGATE2. Connect a well decoupled 5V supply to this pin.
V2_SD
A high level on the V2_SD input places the V
into “sleep” mode. In sleep mode, both UGATE2 and
LGATE2 are driven low, effectively floating the V
PHASE 1
VREF_IN
SENSE1
I
COMP1
DS(ON)
PEAK
DDQ
GNDA
GNDA
VREF
FB1
and V
=
) set the V
1
2
3
4
5
6
7
8
I
------------------------------------------- -
OCS
TT
32
9
r
DS ON
•
regulators are within normal operating
R
(
10
31
OCSET
DDQ
)
32 LEAD 5X5 (QFN)
11
30
converter overcurrent (OC) trip point
TOP VIEW
12
29
13
28
14
27
15
26
16
25
TT
controller
24
23
22
21
20
19
18
17
TT
PVCC1
OCSET/SD
V2_SD
PGOOD
N/C
SENSE2
N/C
VCC
supply.