E-L6258EP

Manufacturer Part NumberE-L6258EP
DescriptionPWM CONTROLLED - HIGH CURRENT DMOS UNIVERSAL MOTOR DRIVER
ManufacturerSTMICROELECTRONICS [STMicroelectronics]
E-L6258EP datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
Page 1/22

Download datasheet (286Kb)Embed
Next
1
FEATURES
ABLE TO DRIVE BOTH WINDINGS OF A
BIPOLAR STEPPER MOTOR OR TWO DC
MOTORS
OUTPUT CURRENT UP TO 1.3A EACH
WINDING
WIDE VOLTAGE RANGE: 12V TO 40V
FOUR QUADRANT CURRENT CONTROL,
IDEAL FOR MICROSTEPPING AND DC
MOTOR CONTROL
PRECISION PWM CONTROL
NO NEED FOR RECIRCULATION DIODES
TTL/CMOS COMPATIBLE INPUTS
CROSS CONDUCTION PROTECTION
THERMAL SHUTDOW
2
DESCRIPTION
L6258EP is a dual full bridge for motor control appli-
cations realized in BCD technology, with the capabil-
ity of driving both windings of a bipolar stepper motor
or bidirectionally control two DC motors.
L6258EP and a few external components form a
Figure 2. Block Diagram
VCP1
CHARGE
PUMP
VREF1
I3_1
I2_1
DAC
I1_1
I0_1
PH_1
V
(5V)
VR GEN
DD
VREF1
I3_2
I2_2
DAC
I1_2
I0_2
PH_2
TRI_CAP
TRIANGLE
GENERATOR
C
FREF
GND
July 2005
PWM CONTROLLED - HIGH CURRENT
DMOS UNIVERSAL MOTOR DRIVER
Figure 1. Package
Table 1. Order Codes
complete control and drive circuit. It has high efficien-
cy phase shift chopping that allows a very low current
ripple at the lowest current control levels, and makes
this device ideal for steppers as well as for DC mo-
tors.The power stage is a dual DMOS full bridge ca-
pable of sustaining up to 40V, and includes the
diodes for current recirculation.The output current ca-
pability is 1.3A per winding in continuous mode, with
peak start-up current up to 2A. A thermal protection
circuitry disables the outputs if the chip temperature
exceeds the safe limits.
R
1M
1
C
C1
R
C1
C
VCP2
EA_IN1
P
ERROR
V
R
AMP
+
INPUT
-
&
SENSE
AMP
THERMAL
V
(V
/2)
R
DD
PROT.
ERROR
V
R
AMP
INPUT
+
&
-
SENSE
AMP
TRI_0
TRI_180
EA_IN2
R
C2
C
R
1M
2
PowerSSO36
Part Number
E-L6258EP
C
BOOT
VS
EA_OUT1
VBOOT
TRI_0
+
OUT1A
C
-
POWER
BRIDGE
+
1
OUT1B
TRI_180
C
-
SENSE1B
R
s
SENSE1A
DISABLE
VS
TRI_0
+
OUT2A
C
-
POWER
BRIDGE
+
2
OUT2B
C
-
SENSE2B
TRI_180
R
s
SENSE2A
EA_OUT2
D96IN430D
C2
L6258EP
DATASHEET
Package
PowerSSO36
Rev. 3
1/22

E-L6258EP Summary of contents

  • Page 1

    ... SENSE AMP THERMAL PROT. ERROR V R AMP INPUT + & - SENSE AMP TRI_0 TRI_180 EA_IN2 PowerSSO36 Part Number E-L6258EP C BOOT VS EA_OUT1 VBOOT TRI_0 + OUT1A C - POWER BRIDGE + 1 OUT1B TRI_180 C - SENSE1B R s SENSE1A DISABLE VS TRI_0 + OUT2A C - POWER BRIDGE ...

  • Page 2

    ... Bootstrap Supply boot Maximum Vgate applicable boot s T Junction Temperature j T Storage Temperature Range stg (1) This current is intended as not repetitive current for max. 1 second. Figure 3. Pin Connection (Top view) PWR_GND PH_1 OUT1A DISABLE TRI_CAP GND VCP1 VCP2 VBOOT OUT2A PH_2 ...

  • Page 3

    ... Negative input of error amplifier (1) 30 EA_OUT_1 Error amplifier output ( See pin 3 2_1 33 I See pin 3 3_1 34 OUT1B Bridge output connection and positive input of the tranconductance (1) Note: The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1 and 36 are connected together. Description L6258EP 3/22 ...

  • Page 4

    ... ERROR AMPLIFIER G Open Loop Voltage Gain V SR Output Slew Rate GBW Gain Bandwidth Product Note 1: This is true for all the logic inputs except the disable input. (*) Chopping frequency is twice fosc value. 4/22 = 40V 5V 25°; unless otherwise specified Test Condition ...

  • Page 5

    ... In figure 4B is shown the timing diagram in the case of positive load current On the contrary want to drive negative current into the load is necessary to decrease the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way we obtain a phase shift between the two ...

  • Page 6

    ... L6258EP Figure 4. Power Bridge Configuration IN_A OUTA OUTB Iload 0 OUTA OUTB Iload 0 OUTA OUTB 0 Iload 6/ LOAD OUT_A OUT_B T3 T4 IN_B Fig. 4A Fig. 4B Fig. 4C D97IN624 ...

  • Page 7

    ... Figure 5. Current Control Loop Block Diagram INPUT TRANSCONDUCTANCE AMPL. ia VREF DAC VDAC - Gin=1/Ra 3.2 Input Logic ( The current level in the motor winding is selected according to this table: Table ...

  • Page 8

    ... 3.5 Charge Pump Circuit To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on the Vboot pin. This boostrap voltage is not needed for the low side power DMOS transistors because their sources terminals are grounded. To produce this voltage a charge pump method is used made by using two external capacitors; ...

  • Page 9

    ... OUT_A through the motor winding to OUT_B. With a negative differential voltage V In this case the output of the first comparator is a square wave with a duty cycle lower than 50%, while the output of the second comparator is a square wave with a duty cycle higher than 50%. ...

  • Page 10

    ... Internal reference equal these data refer to a typical application, and will be used as an example during the analysis of the stability of the current control loop. The block diagram shows the schematics of the L6258EP internal current control loop working in PWM mode; the current into the load is a function of the input control voltage V ...

  • Page 11

    ... Tri_0 and Tri_180. Because all the current control loop is referred to the Vr refer- ence, the result is that when the output voltage of the error amplifier is equal to the Vr voltage the two output Out_A and Out_B have the same phase and duty cycle at 50%; increasing the output voltage of the error am- plifier above the Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases of the same percentage ...

  • Page 12

    ... L6258EP so the gain of this block is: where equivalent resistance of the motor winding sense resistor S Because of the inductance of the motor L Before analysing the error amplifier block and the sense transconductance block, we have to do this consider- ation : Aloop = Ax| = ACpw| + ACload| ...

  • Page 13

    ... The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz clear now that (because of the negative gain of the Ax function), Bx function must have an high DC gain in order to increment the total open loop gain increasing the bandwidth too. 4.4 Error Amplifier and Sense Amplifier ...

  • Page 14

    ... L6258EP The transfer function of the Bx block with the compensation on the error amplifier this case the Bx block has a DC gain equal to the open loop and equal to zero at a frequency given by the following formula: In order to cancel the pole of the load, the zero of the Bx block must be located at the same frequency of 163Hz; ...

  • Page 15

    ... We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total Aloop cross a the 0dB axis with a slope of -20dB/decade, having in this way a stable system with an high gain at low frequency and a bandwidth of around 8KHz. To increase the bandwidth of the system, we should increase the gain of the Bx block, keeping the zero in the same position ...

  • Page 16

    ... A decoupling capacitor of 100nF is suggested also between the logic supply and ground. The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to avoid coupled noise on this signals. The suggestion is to put the components connected to this pins close to the L6258EP, to surround them with ground tracks and to keep as far as possible fast switching outputs of the device ...

  • Page 17

    ... It's important to separate on the PCB board the logic and power grounds and the internal charge pump circuit ground avoiding that ground traces of the logic signals cross the ground traces of the power signals. Because the IC uses the board as a heat sink, the dissipating copper area must be sized in accordance with the required value of R ...

  • Page 18

    ... L6258EP Figure 13. Half step operation mode timing diagram (Phase - DAC input and Motor Current Phase Phase I0_1 0 5V DAC 1 I1_1 0 Inputs 5V I2_1 0 5V I3_1 0 5V I0_2 0 5V I1_2 DAC 2 0 Inputs 5V I2_2 0 5V I3_2 0 100% 71.4% 0 Motor drive Current 1 -71 ...

  • Page 19

    ... Figure 14. 4 bit microstep operation mode timing diagram (Phase - DAC input and Motor Current) Position Phase Phase 5V 2 I0_1 0 5V I1_1 0 DAC 1 Inputs 5V I2_1 0 5V I3_1 0 5V I0_2 0 DAC 2 Inputs 5V I1_2 0 5V I2_2 0 I3_2 0 Motor drive ...

  • Page 20

    ... M 4.3 N 10˚ O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 X 4.1 4.7 Y 6.5 7.3 (1) "D” and “E" do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0.15 mm per side(0.006”) G LEAD COPLANARITY 0 20/22 inch MIN. TYP. MAX. 0.084 0.097 0.084 0.094 0 0.003 0.007 ...

  • Page 21

    ... Table 8. Revision History Date Revision February 2005 March 2005 July 2005 1 First Issue in the EDOCS DMS. 2 Modified the note “(1)” of the Table 2. 3 Changed the maturity from Preliminary data to datasheet. Modified in Table 4 the Voffset parameter values. Description of Changes L6258EP 21/22 ...

  • Page 22

    ... STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America ...