LMH0030_0608 NSC [National Semiconductor], LMH0030_0608 Datasheet

LMH0030_0608

Manufacturer Part Number

LMH0030_0608

Description

SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver

Manufacturer

NSC [National Semiconductor]

Datasheet

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LMH0030

SMPTE 292M/259M Digital Video Serializer with Video

and Ancillary Data FIFOs and Integrated Cable Driver

General Description

The LMH0030 SMPTE 292M/259M Digital Video Serializer

with Ancillary Data FIFO and Integrated Cable Driver is a

monolithic integrated circuit that encodes, serializes and

transmits bit-parallel digital video data conforming to SMPTE

125M and 267M standard definition, 10-bit wide component

video and SMPTE 260M, 274M, 295M and 296M high-

definition, 20-bit wide component video standards. The

LMH0030 operates at SMPTE 259M serial data rates of

270 Mbps, 360 Mbps, the SMPTE 344M serial data rate of

540 Mbps, and the SMPTE 292M serial data rates of 1483.5

and 1.485 Gbps. The serial data clock frequency is internally

generated and requires no external frequency setting, trim-

ming or filtering components.

The LMH0030 performs functions which include: parallel-to-

serial data conversion, SMPTE standard data encoding,

NRZ to NRZI data format conversion, serial data clock gen-

eration and encoding with the serial data, automatic video

rate and format detection, ancillary data packet manage-

ment and insertion, and serial data output driving. The

LMH0030 has circuitry for automatic EDH/CRC character

and flag generation and insertion per SMPTE RP-165 (stan-

dard definition) or SMPTE 292M (high definition). Optional

LSB dithering is implemented which prevents pathological

pattern generation. Unique to the LMH0030 are its video and

ancillary data FIFOs. The video FIFO allows the video data

to be delayed from 0 to 4 parallel data clock periods for video

timing purposes. The ancillary data port and on-chip FIFO

and control circuitry store and insert ancillary flags, data

packets and checksums into the ancillary data space. The

LMH0030 also has an exclusive built-in self-test (BIST) and

video test pattern generator (TPG) with SD and HD compo-

nent video test patterns: reference black, PLL and EQ patho-

logicals and color bars in 4:3 and 16:9 raster formats for

NTSC and PAL standards*. The color bar patterns feature

optional bandwidth limiting coding in the chroma and luma

transitions.

The LMH0030 has a unique multi-function I/O port for imme-

diate access to control and configuration settings. This port

may be programmed to provide external access to control

functions and indicators as inputs and outputs. The designer

can thus customize the LMH0030 to fit the desired applica-

tion. At power-up or after a reset command, the LMH0030 is

auto-configured to a default operating condition. Separate

power pins for the output driver, PLL and the serializer

improve power supply rejection, output jitter and noise per-

formance.

Order Number LMH0030VS

DS201803

64-Pin TQFP

The LMH0030’s internal circuitry is powered from +2.5V and

the I/O circuitry from a +3.3V supply. Power dissipation is

typically 430mW at 1.485 Gbps including two 75Ω AC-

coupled and back-matched output loads. The device is pack-

aged in a 64-pin TQFP.

Features

n SDTV/HDTV serial digital video standard compliant

n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps

n Low output jitter: 125ps max, 85ps typical

n Low power: typically 430mW

n No external serial data rate setting or VCO filtering

n Fast PLL lock time:

n Adjustable depth video FIFO for timing alignment

n Built-in self-test (BIST) and video test pattern generator

n Automatic EDH/CRC word and flag generation and

n On-chip ancillary data FIFO and insertion control

n Flexible control and configuration I/O port

n LVCMOS compatible data and control inputs and

n 75Ω ECL-compatible, differential, serial cable-driver

n 3.3V I/O power supply and 2.5V logic power supply

n 64-pin TQFP package

* Patent applications made or pending.

Applications

n SDTV/HDTV parallel-to-serial digital video interfaces for:

and 1.485 Gbps SDV data rates with auto-detection

components required*

(TPG)*

insertion

circuitry

outputs

operation

— Video cameras

— VTRs

— Telecines

— Digital video routers and switchers

— Digital video processing and editing equipment

— Video test pattern generators and digital video test

— Video signal generators

equipment

NS Package Number VEC-64A

150µs typical at 1.485 Gbps

www.national.com

August 2006

Related parts for LMH0030_0608

LMH0030_0608 Summary of contents

Page 1

LMH0030 SMPTE 292M/259M Digital Video Serializer with Video and Ancillary Data FIFOs and Integrated Cable Driver General Description The LMH0030 SMPTE 292M/259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver is a monolithic integrated circuit that encodes, ...

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Typical Application www.national.com 2 20180301 ...

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Block Diagram 3 20180302 www.national.com ...

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Connection Diagram www.national.com 64-Pin TQFP Order Number LMH0030VS See NS Package Number VEC-64A 4 20180303 ...

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Absolute Maximum Ratings is anticipated that this device will not be offered in a military qualified version. If Military/Aerospace specified devices are required, please contact the National Semicon- ductor Sales Office / Distributors for availability and specifi- cations. CMOS I/O ...

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DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3). Symbol Parameter I (3.3V) Power Supply Current, DD 3.3V Supply, Total I (2.5V) Power Supply Current, DD 2.5V Supply, Total I (2.5V) Power Supply ...

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AC Electrical Characteristics Note 8: Average value measured between rising edges computed over at least one video field. Note 9: Intrinsic timing jitter is measured in accordance with SMPTE RP 184-1996, SMPTE RP 192-1996 and the applicable serial data transmission ...

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Test Circuit www.national.com 8 20180307 ...

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Timing Diagram Device Operation The LMH0030 SDTV/HDTV Serializer is used in digital video signal origination equipment: cameras, video tape recorders, telecines and video test and other equipment. It converts parallel SDTV or HDTV component digital video signals into serial format. ...

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Device Operation (Continued) The ACLK input controls data flow through the port. The operation and frequency of ACLK is independent of the video data clock, VCLK. However, the frequency of ACLK must be less than or equal to VCLK. There ...

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Device Operation (Continued) CONTROL DATA WRITE FUNCTIONS Figure 2 shows the sequence of clock and control signals for writing control data to the ancillary/control data port. The control data write mode is similar to the read mode. The control data ...

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Device Operation (Continued) Writing of ancillary data to the FIFO, packet handling and insertion into the video data stream are controlled by a MULTI-FUNCTION I/O PORT The Multi-function I/O port can be configured to provide immediate access to many control ...

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Device Operation (Continued) supplied power via external low-pass filters, if desired. PLL @ acquisition time is less than 200µs 1485 Mbps. The VCO halts when the V signal is not present or is inactive. CLK A LOCK DETECT indicator function ...

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Device Operation (Continued) logic-0. The TPG or BIST is halted by resetting TPG Enable. The serial output data is present at the SDO outputs during TPG or BIST operation. Caution ! When attempting to use the TPG or BIST imme- ...

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Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary Register Function Bits EDH Error (SD) 1 Full-Field Flags 5 Active Picture Flags 5 ANC Flags 5 EDH Force 1 EDH Enable 1 F/F Flag Error 1 A/P Flag ...

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Device Operation (Continued) TABLE 1. Configuration and Control Data Register Summary (Continued) Register Function Bits Scrambler_ Enable 1 NRZI_Enable 1 LSB_Clipping 1 SYNC_Detect_Enable 1 I/O Bus Pin Config. 48 Note 12: Connected to multifunction I/O port at power-on. Note 13: ...

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Device Operation (Continued) TABLE 2. Control Register Bit Assignments (Continued) Bit 7 Bit 6 Bit TEST 0 (register address 0Dh) TEST PASS/FAIL TPG ENABLE PATTERN SELECT(5) VIDEO INFO 0 (register address 0Eh) VERT. DITHER VPG FILTER DITHER ...

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Device Operation (Continued) TABLE 3. Control Register Addresses Address Register Name Decimal EDH 0 1 EDH 1 2 EDH 2 3 ANC 0 4 ANC 1 5 ANC 2 6 ANC 3 7 ANC 4 8 ANC 5 23 ANC ...

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Device Operation (Continued) The ANC Checksum Error bit indicates that the received ancillary data checksum did not agree with the LMH0030’s internally generated checksum. This bit is available as an output on the multifunction I/O port. ANC REGISTERS 1 THROUGH ...

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Device Operation (Continued) Format Code Format Specification [4,3,2,1,0] 00001 SDTV, 54 SMPTE 344M 00010 SDTV, 36 SMPTE 267M 00011 SDTV, 27 SMPTE 125M 01001 SDTV, 54 ITU-R BT 601.5 01010 SDTV, 36 ITU-R BT 601.5 01011 SDTV, 27 ITU-R BT ...

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Device Operation (Continued) the insertion of transition codes in the chroma and luma data of color bar test patterns where these patterns change from one bar to the next. This filter reduces the magnitude of out-of-band frequency products which can ...

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Device Operation (Continued) Test Pattern Bit 5 Select Word > Bits 1=HD 1=Progressive 0=Interlaced Video Raster Standard 0=SD 1=PAL 0=NTSC 1125 Line, 74.25 MHz, 30 Frame Interlaced Component (SMPTE 260M) Ref. Black 1 PLL Path Path. 1 color ...

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Device Operation (Continued) TABLE 5. Test Pattern Selection Codes (Continued) Test Pattern Bit 5 Select Word > Bits 525 Line, 30 Frame, 27 MHz, NTSC 4x3 (SMPTE 125M) Ref. Black 0 PLL Path Path. 0 color Bars (SD ...

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Device Operation (Continued) TABLE 6. I/O Configuration Register Addresses for Control Register Functions Register Bit [5] [4] reserved Flag 0 0 Error AP Flag 0 0 Error ANC Flag 0 0 Error CRC Error 0 0 (SD/HD) ...

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Device Operation (Continued) TABLE 6. I/O Configuration Register Addresses for Control Register Functions (Continued) Register Bit [5] [4] Chksum 1 0 Attach In reserved 1 0 VPG Filter 1 0 Enable Dither 1 0 Enable FIFO Insert 1 0 Enable ...

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Pin Descriptions Pin Name 1 V DDPLLD 2 V SSPLLD 3 IO0 4 IO1 5 DV0 6 DV1 7 DV2 8 DV3 9 DV4 10 V SSD 11 DV5 12 DV6 13 DV7 14 DV8 15 DV9 16 V DDD ...

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Pin Descriptions (Continued) Pin Name 50 ANC/CTRL 51 V DDSD 52 R PRE REF 53 R LVL REF 54 V SSSD 55 V SSSD 56 SDO 57 V DDLS 58 SDO 59 V SSLS 60 V DDZ 61 V SSPLLA ...

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Application Information Complete details for the SD130ASM evaluation PCB are available on National’s WEB site. This circuit demonstrates the capabilities of the LMH0030 and allows its evaluation in a native configuration. An assembled demonstration board kit, part number SD130EVK, complete ...

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Physical Dimensions inches (millimeters) unless otherwise noted National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and ...

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