ADT7476ARQH ONSEMI [ON Semiconductor], ADT7476ARQH Datasheet - Page 24

• Manufacturer Part Number: ADT7476ARQH
• Description: dBCOOL Remote Thermal Controller and Voltage Monitor
• Manufacturer: ONSEMI [ON Semiconductor]

When using the THERM timer, be aware of the following:
After a THERM timer read (0x79)
If the THERM timer is read during a THERM assertion, the
following occurs:
1. The contents of the timer are cleared on read.
2. The F4P bit (Bit 5) of Interrupt Status Register 2
1. The contents of the timer are cleared.
Figure 32. Understanding the THERM Timer
(REG. 0x79)
(REG. 0x79)
(REG. 0x79)
needs to be cleared (assuming that the THERM
timer limit has been exceeded).
THERM
THERM
THERM
THERM
THERM
THERM
TIMER
TIMER
TIMER
ACCUMULATE THERM LOW
ACCUMULATE THERM LOW
THERM LIMIT
ASSERTION TIMES
ASSERTION TIMES
(REG. 0x7A)
0 0 0
7 6 5
0 0 0
7 6 5
0 0 0
7 6 5
0
4
0
4
0
4
0 0 0 1
3 2 1 0
0 0 1 0
3 2 1 0
0 1 0 1
3 2 1 0
728.32ms
364.16ms
182.08ms
Figure 33. Functional Block Diagram of THERM Monitoring Circuitry
91.04ms
45.52ms
22.76ms
2.914s
1.457s
THERM ASSERTED w 113.8ms
(91.04ms + 22.76ms)
THERM ASSERTED
THERM ASSERTED
0
v 22.76ms
w 45.52ms
1
2
3
4
5
6
COMPARATOR
7
http://onsemi.com
CLEARED
ON READ
24
7 6 5 4 3 2 1 0
IN
Generating SMBALERT Interrupts from THERM Timer
Events
programmable THERM timer limit has been exceeded. This
allows the system designer to ignore brief, infrequent
THERM assertions, while capturing longer THERM timer
events. Register 0x7A is the THERM timer limit register.
This 8−bit register allows a limit from 0 sec (first THERM
assertion) to 5.825 sec to be set before an SMBALERT is
generated. The THERM timer value is compared with the
contents of the THERM timer limit register. If the THERM
timer value exceeds the THERM timer limit value, then the
F4P bit (Bit 5) of Interrupt Status Register 2 is set and an
SMBALERT is generated.
THERM timer, setting the F4P bit (Bit 5) of Mask Register 2
(0x75) or Bit 0 of Mask Register 1 (0x74) masks out
SMBALERT; although the F4P bit of Interrupt Status
Register 2 is still set if the THERM timer limit is exceeded.
timer, limit, and associated circuitry. Writing a value of 0x00
to the THERM timer limit register (0x7A) causes an
SMBALERT to be generated on the first THERM assertion.
A THERM timer limit value of 0x01 generates an
SMBALERT once cumulative THERM assertions exceed
45.52 ms.
LATCH
RESET
The ADT7476 can generate SMBALERTs when a
Note: Depending on which pins are configured as a
Figure 33 is a functional block diagram of the THERM
OUT
2. Bit 0 of the THERM timer is set to 1, because a
3. The THERM timer increments from zero.
4. If the THERM timer limit register (0x7A) = 0x00,
1 = MASK
THERM assertion is occurring.
the F4P bit is set.
MASK REGISTER 2
STATUS REGISTER 2
F4P BIT (BIT 5)
(REG. 0x75)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
1.457s
182.08ms
2.914s
728.32ms
364.16ms
91.04ms
45.52ms
22.76ms
THERM TIMER
(REG. 0x79)
SMBALERT
THERM